Hi Marek
On 3/31/20 2:48 AM, Marek Vasut wrote:
The PLL4 is supplying SDMMC12, SDMMC3 and SPDIF with 120 MHz and FDCAN with 96 MHz. This isn't good for the SDMMC interfaces, which can not easily divide the clock down to e.g. 50 MHz for high speed SD and eMMC devices, so those devices end up running at 30 MHz as that is 120 MHz / 4. Adjust the PLL4 settings such that both PLL4P and PLL4R run at 100 MHz instead, which is easy to divide to 50MHz for optimal operation of both SD and eMMC, SPDIF clock are not that much slower and FDCAN is also unaffected.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
V2: Move this patch before the split of AV96 into SoM and carrier
arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index 2c7dc509a3..320132a01e 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -130,11 +130,11 @@ u-boot,dm-pre-reloc; };
- /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
- /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>;
cfg = < 1 39 3 11 4 PQR(1,1,1) >;
cfg = < 1 49 5 11 5 PQR(1,1,1) >;};