Add additional defines for the reset manager for different reset status bits.
Signed-off-by: Dinh Nguyen dinguyen@kernel.org --- arch/arm/mach-socfpga/include/mach/reset_manager.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 2f070f2..9750026 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -79,4 +79,25 @@ struct socfpga_reset_manager { /* Create a human-readable reference to SoCFPGA reset. */ #define SOCFPGA_RESET(_name) RSTMGR_##_name
+#define RSTMGR_STAT_L4WD1RST_MASK 0x00008000 +#define RSTMGR_STAT_L4WD0RST_MASK 0x00004000 +#define RSTMGR_STAT_MPUWD1RST_MASK 0x00002000 +#define RSTMGR_STAT_MPUWD0RST_MASK 0x00001000 +#define RSTMGR_STAT_SWWARMRST_MASK 0x00000400 +#define RSTMGR_STAT_FPGAWARMRST_MASK 0x00000200 +#define RSTMGR_STAT_NRSTPINRST_MASK 0x00000100 +#define RSTMGR_STAT_SWCOLDRST_MASK 0x00000010 +#define RSTMGR_STAT_CONFIGIOCOLDRST_MASK 0x00000008 +#define RSTMGR_STAT_FPGACOLDRST_MASK 0x00000004 +#define RSTMGR_STAT_NPORPINRST_MASK 0x00000002 +#define RSTMGR_STAT_PORVOLTRST_MASK 0x00000001 + +#define RSTMGR_WARMRST_MASK (RSTMGR_STAT_SWWARMRST_MASK | \ + RSTMGR_STAT_L4WD0RST_MASK | \ + RSTMGR_STAT_L4WD1RST_MASK | \ + RSTMGR_STAT_MPUWD1RST_MASK | \ + RSTMGR_STAT_MPUWD0RST_MASK | \ + RSTMGR_STAT_FPGAWARMRST_MASK | \ + RSTMGR_STAT_NRSTPINRST_MASK) + #endif /* _RESET_MANAGER_H_ */