Signed-off-by: Tom Rini trini@konsulko.com --- README | 2 +- arch/arm/cpu/armv7/s5p4418/cpu.c | 2 +- board/armltd/total_compute/total_compute.c | 2 +- board/armltd/vexpress64/vexpress64.c | 2 +- drivers/serial/serial_pl01x.c | 8 ++++---- include/configs/corstone1000.h | 2 +- include/configs/highbank.h | 2 +- include/configs/lx2160a_common.h | 2 +- include/configs/mxs.h | 2 +- include/configs/s5p4418_nanopi2.h | 2 +- include/configs/synquacer.h | 2 +- include/configs/thunderx_88xx.h | 2 +- include/configs/total_compute.h | 2 +- include/configs/vexpress_aemv8.h | 4 ++-- include/configs/vexpress_common.h | 2 +- scripts/config_whitelist.txt | 2 +- 16 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/README b/README index d3659e7b54a2..1eda285312be 100644 --- a/README +++ b/README @@ -419,7 +419,7 @@ The following options need to be configured: controller register space
- Serial Ports: - CONFIG_PL011_CLOCK + CFG_PL011_CLOCK
If you have Amba PrimeCell PL011 UARTs, set this variable to the clock speed of the UARTs. diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 3baa761ec7a9..7ba9c0b03236 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -64,7 +64,7 @@ static void serial_device_init(void)
/* set clock */ clk_disable(clk); - clk_set_rate(clk, CONFIG_PL011_CLOCK); + clk_set_rate(clk, CFG_PL011_CLOCK); clk_enable(clk); } #endif diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index b7772f79a31a..53941b5f5f28 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -13,7 +13,7 @@ static const struct pl01x_serial_plat serial_plat = { .base = UART0_BASE, .type = TYPE_PL011, - .clock = CONFIG_PL011_CLOCK, + .clock = CFG_PL011_CLOCK, };
U_BOOT_DRVINFO(total_compute_serials) = { diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 4ca544f1017d..99fb67ecedc2 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; static const struct pl01x_serial_plat serial_plat = { .base = V2M_UART0, .type = TYPE_PL011, - .clock = CONFIG_PL011_CLOCK, + .clock = CFG_PL011_CLOCK, };
U_BOOT_DRVINFO(vexpress_serials) = { diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index d3c3d3e2d188..dd2881931dfd 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -193,7 +193,7 @@ static void pl01x_serial_init_baud(int baudrate)
#if defined(CONFIG_PL011_SERIAL) pl01x_type = TYPE_PL011; - clock = CONFIG_PL011_CLOCK; + clock = CFG_PL011_CLOCK; #endif base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
@@ -343,8 +343,8 @@ static const struct udevice_id pl01x_serial_id[] ={ {} };
-#ifndef CONFIG_PL011_CLOCK -#define CONFIG_PL011_CLOCK 0 +#ifndef CFG_PL011_CLOCK +#define CFG_PL011_CLOCK 0 #endif
int pl01x_serial_of_to_plat(struct udevice *dev) @@ -359,7 +359,7 @@ int pl01x_serial_of_to_plat(struct udevice *dev) return -EINVAL;
plat->base = addr; - plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK); + plat->clock = dev_read_u32_default(dev, "clock", CFG_PL011_CLOCK); ret = clk_get_by_index(dev, 0, &clk); if (!ret) { ret = clk_enable(&clk); diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h index 8aec52d508e2..3347c11792d5 100644 --- a/include/configs/corstone1000.h +++ b/include/configs/corstone1000.h @@ -16,7 +16,7 @@
#define V2M_BASE 0x80000000
-#define CONFIG_PL011_CLOCK 50000000 +#define CFG_PL011_CLOCK 50000000
/* Physical Memory Map */ #define PHYS_SDRAM_1 (V2M_BASE) diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 76e6054b0cc1..97bb439f7357 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -8,7 +8,7 @@
#define CFG_SYS_BOOTMAPSZ (16 << 20)
-#define CONFIG_PL011_CLOCK 150000000 +#define CFG_PL011_CLOCK 150000000
/* * Miscellaneous configurable options diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 0fc32efabc7f..ea59f772064a 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -41,7 +41,7 @@
/* Serial Port */ -#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) +#define CFG_PL011_CLOCK (get_bus_freq(0) / 4) #define CFG_SYS_SERIAL0 0x21c0000 #define CFG_SYS_SERIAL1 0x21d0000 #define CFG_SYS_SERIAL2 0x21e0000 diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 30f27e7f0c19..212d2201e7cc 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -77,7 +77,7 @@ * DUART Serial Driver. * Conflicts with AUART driver which can be set by board. */ -#define CONFIG_PL011_CLOCK 24000000 +#define CFG_PL011_CLOCK 24000000 #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } /* Default baudrate can be overridden by board! */
diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index 02c469049adb..c9cef6a77c62 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -78,7 +78,7 @@ /*----------------------------------------------------------------------- * serial console configuration */ -#define CONFIG_PL011_CLOCK 50000000 +#define CFG_PL011_CLOCK 50000000 #define CONFIG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \ (void *)PHY_BASEADDR_UART1, \ (void *)PHY_BASEADDR_UART2, \ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index fa522ce82883..d0b56cb48f7d 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -32,7 +32,7 @@
/* Serial (pl011) */ #define UART_CLK (62500000) -#define CONFIG_PL011_CLOCK UART_CLK +#define CFG_PL011_CLOCK UART_CLK #define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
/* Support MTD */ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 8ba40546b2c0..2bca86bed939 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -17,7 +17,7 @@
/* PL011 Serial Configuration */
-#define CONFIG_PL011_CLOCK 24000000 +#define CFG_PL011_CLOCK 24000000
/* Generic Interrupt Controller Definitions */ #define GICD_BASE (0x801000000000) diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index e007be8e4564..436bf622e174 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -14,7 +14,7 @@ #define UART0_BASE 0x7ff80000
/* PL011 Serial Configuration */ -#define CONFIG_PL011_CLOCK 7372800 +#define CFG_PL011_CLOCK 7372800
/* Miscellaneous configurable options */
diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 87b8c5d57ee7..43f7e454d812 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -86,9 +86,9 @@
/* PL011 Serial Configuration */ #ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_PL011_CLOCK 7372800 +#define CFG_PL011_CLOCK 7372800 #else -#define CONFIG_PL011_CLOCK 24000000 +#define CFG_PL011_CLOCK 24000000 #endif
/* Physical Memory Map */ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 705a941e3603..3fc70de57713 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -116,7 +116,7 @@ #define CFG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
/* PL011 Serial Configuration */ -#define CONFIG_PL011_CLOCK 24000000 +#define CFG_PL011_CLOCK 24000000 #define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ (void *)CFG_SYS_SERIAL1}
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 3e9d0d66f56d..0ea10f2edb32 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -158,7 +158,7 @@ CFG_PHY_ET1011C_TX_CLK_FIX CFG_PHY_ID CFG_PHY_INTERFACE_MODE CFG_PHY_IRAM_BASE -CONFIG_PL011_CLOCK +CFG_PL011_CLOCK CONFIG_PL01x_PORTS CONFIG_PME_PLAT_CLK_DIV CONFIG_POST