Fifo width could be different on different socs, e.g. stv0991 & altera soc have different fifo width.
Signed-off-by: Vikas Manocha vikas.manocha@st.com --- arch/arm/dts/socfpga.dtsi | 1 + arch/arm/dts/stv0991.dts | 1 + drivers/spi/cadence_qspi.c | 1 + drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 13 ++++--------- 5 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index d89c974..a2a2029 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -640,6 +640,7 @@ ext-decoder = <0>; /* external decoder */ num-cs = <4>; fifo-depth = <128>; + fifo-width = <4>; bus-num = <2>; status = "disabled"; }; diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts index 72399ff..433fcd1 100644 --- a/arch/arm/dts/stv0991.dts +++ b/arch/arm/dts/stv0991.dts @@ -36,6 +36,7 @@ ext-decoder = <0>; /* external decoder */ num-cs = <4>; fifo-depth = <256>; + fifo-width = <8>; bus-num = <0>; status = "okay";
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index b23461d..dfdd9e3 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -310,6 +310,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255); plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20); plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); + plat->fifo_width = fdtdec_get_int(blob, node, "fifo-width", 4);
debug("%s: regbase=%p flashbase=%p trigger_base=%p max-frequency=%d \ page-size=%d\n", __func__, plat->regbase, plat->flashbase, diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 5ea4581..2be1b43 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -26,6 +26,7 @@ struct cadence_spi_platdata { u32 tsd2d_ns; u32 tchsh_ns; u32 tslch_ns; + u32 fifo_width; };
struct cadence_spi_priv { diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 2994158..61fc95a 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -34,8 +34,6 @@ #define CQSPI_REG_RETRY (10000) #define CQSPI_POLL_IDLE_RETRY (3)
-#define CQSPI_FIFO_WIDTH (4) - /* Controller sram size in word */ #define CQSPI_REG_SRAM_SIZE_WORD (128) #define CQSPI_REG_SRAM_RESV_WORDS (2) @@ -54,9 +52,6 @@ #define CQSPI_DUMMY_CLKS_PER_BYTE (8) #define CQSPI_DUMMY_BYTES_MAX (4)
- -#define CQSPI_REG_SRAM_FILL_THRESHOLD \ - ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH) /**************************************************************************** * Controller's configuration and status register (offset from QSPI_BASE) ****************************************************************************/ @@ -235,11 +230,11 @@ static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat, page_size : remaining;
remaining -= wr_bytes; - while (wr_bytes >= CQSPI_FIFO_WIDTH) { - for (i = 0; i < CQSPI_FIFO_WIDTH/sizeof(dest_addr); i++) + while (wr_bytes >= plat->fifo_width) { + for (i = 0; i < plat->fifo_width/sizeof(dest_addr); i++) writel(*(src_ptr+i), dest_addr+i); - src_ptr += CQSPI_FIFO_WIDTH/sizeof(dest_addr); - wr_bytes -= CQSPI_FIFO_WIDTH; + src_ptr += plat->fifo_width/sizeof(dest_addr); + wr_bytes -= plat->fifo_width; } if (wr_bytes) { /* dangling bytes */