The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch implements these three bootup methods in a unified way - all of these use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM which lets us use the SPD to initialize the SDRAM.
For all three bootup methods, the bootup process can be divided into two stages: the first stage will initialize the corresponding controller, configure the L2SRAM, then copy the second stage image to L2SRAM and jump to it. The second stage image is just like the general U-Boot image to configure all the hardware and boot up to U-Boot command line.
When boot from NAND, the eLBC controller will first load the first stage image to internal 4K RAM buffer because it's also stored on the NAND flash. The first stage image, also call 4K NADN loader, will initialize the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K NAND loader's code comes from the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL.
When boot from eSDHC/eSPI, there's no such a first stage image because the CPU ROM code does the same work. It will initialize the L2SRAM according to the config addr/word pairs on the fixed address and initialize the eSDHC/eSPI controller, then load the second stage image to L2SRAM and jump to it.
The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the second stage image for all different bootup methods. It's set in the board config file when one of the bootup methods above is selected.
Signed-off-by: Mingkai Hu Mingkai.hu@freescale.com --- cpu/mpc85xx/cpu_init.c | 19 +++++++++++++++++++ cpu/mpc85xx/start.S | 23 ++++++++++++++++++++++- cpu/mpc85xx/tlb.c | 4 ++++ drivers/misc/fsl_law.c | 2 ++ 4 files changed, 47 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index c4d1a9d..c931d4a 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -291,6 +291,25 @@ int cpu_init_r(void)
asm("msync;isync"); cache_ctl = l2cache->l2ctl; + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + if (cache_ctl & MPC85xx_L2CTL_L2E) { + /* Clear L2 SRAM memory-mapped base address */ + out_be32(&l2cache->l2srbar0, 0x0); + out_be32(&l2cache->l2srbar1, 0x0); + + /* set MBECCDIS=0, SBECCDIS=0 */ + clrbits_be32(&l2cache->l2errdis, + (MPC85xx_L2ERRDIS_MBECC | + MPC85xx_L2ERRDIS_SBECC)); + + /* set L2E=0, L2SRAM=0 */ + clrbits_be32(&l2cache->l2ctl, + (MPC85xx_L2CTL_L2E | + MPC85xx_L2CTL_L2SRAM_ENTIRE)); + } +#endif + l2siz_field = (cache_ctl >> 28) & 0x3;
switch (l2siz_field) { diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 4f7236f..de13c25 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -57,10 +57,12 @@ GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(_FIXUP_TABLE_)
+#ifndef CONFIG_NAND_SPL GOT_ENTRY(_start) GOT_ENTRY(_start_of_vectors) GOT_ENTRY(_end_of_vectors) GOT_ENTRY(transfer_to_handler) +#endif
GOT_ENTRY(__init_end) GOT_ENTRY(_end) @@ -235,10 +237,11 @@ _start_e500:
#endif /* CONFIG_MPC8569 */
- /* create a temp mapping in AS=1 to the 4M boot window */ lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
+#ifndef CONFIG_SYS_RAMBOOT + /* create a temp mapping in AS=1 to the 4M boot window */ lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
@@ -248,6 +251,20 @@ _start_e500: /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#else + /* + * create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main + * image has been relocated to TEXT_BASE on the second stage. + */ + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l + + lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l + + lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#endif
mtspr MAS0,r6 mtspr MAS1,r7 @@ -359,6 +376,7 @@ _start_cont: bl board_init_f isync
+#ifndef CONFIG_NAND_SPL . = EXC_OFF_SYS_RESET .globl _start_of_vectors _start_of_vectors: @@ -813,6 +831,7 @@ in32: in32r: lwbrx r3,r0,r3 blr +#endif /* !CONFIG_NAND_SPL */
/*------------------------------------------------------------------------------*/
@@ -975,6 +994,7 @@ clear_bss: mr r4,r10 /* Destination Address */ bl board_init_r
+#ifndef CONFIG_NAND_SPL /* * Copy exception vector code to low memory * @@ -1122,3 +1142,4 @@ flush_dcache: isync
blr +#endif /* !CONFIG_NAND_SPL */ diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 46925f1..962c4c7 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -59,6 +59,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, #endif }
+#ifndef CONFIG_NAND_SPL void disable_tlb(u8 esel) { u32 _mas0, _mas1, _mas2, _mas3, _mas7; @@ -83,6 +84,7 @@ void disable_tlb(u8 esel) addrmap_set_entry(0, 0, 0, esel); #endif } +#endif
void invalidate_tlb(u8 tlb) { @@ -125,6 +127,7 @@ void init_addr_map(void) } #endif
+#ifndef CONFIG_NAND_SPL #ifndef CONFIG_SYS_DDR_TLB_START #define CONFIG_SYS_DDR_TLB_START 8 #endif @@ -172,3 +175,4 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) */ return memsize_in_meg; } +#endif /* !CONFIG_NAND_SPL */ diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index f7d454d..473d196 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -72,6 +72,7 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) return idx; }
+#ifndef CONFIG_NAND_SPL int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { u32 idx; @@ -164,6 +165,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
return 0; } +#endif
void init_laws(void) {