
Hi,
I was thinking of this and we might need to introduce either special accessor for this particular register or rework include/regs-common.h and introduce mx28_reg_8 (which I don't think is a good idea).
I tend to agree with you about introducing mx28_reg_8. It doesn't 'feel right' because it violates the orthogonality of it. But I'm afraid there's no other solution because mx28_reg_32 implies 32-bit access, while it is in fact not allowed.
I also think the manual should have specified these registers as separate 8-bit wide registers, preventing confusion and allowing for more appropriate bit-field names.
So Robert, what do you think about introducing a special accessor in include/regs-clkctrl for FRAC0/1? This though introduces a problem with usage of _set, _clk and _tog accesses, which might need a little thinking through.
I agree and I'm considering that now. I'm afraid there's no elegant solution for this. Suggestions are welcome.
Thanks for this patch, you really did a good share of research on this one.
You're welcome. I now have some grasp on how the clock-tree works, but unfortunately still no 100% full understanding. What also bugs me is that I cannot explain why the board continues to work when bypass is disabled on an ill-configured pll. I'm afraid this code still needs some love and attention before it's 100% right.
Cheers,
Robert.