--- /dev/null +++ b/cpu/arm_cortexa8/s5pc100/cpu_init.S
please rename it lowlevel_init.S
@@ -0,0 +1,196 @@ +/*
- Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
- Copyright (C) 2008
- Guennadi Liakhovetki, DENX Software Engineering, lg@denx.de
- Copyright (C) 2009
- Inki Dae, SAMSUNG Electronics, inki.dae@samsung.com
- Heungjun Kim, SAMSUNG Electronics, riverful.kim@samsung.com
- Minkyu Kang, SAMSUNG Electronics, mk7.kang@samsung.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <config.h>
- .globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+#ifdef CONFIG_ONENAND_IPL
please use CONFIG_PRELODER as it will also be used for NAND_SPL and so on please only use ONENAND_IPL when it will be OneNand specific
- /* DLL parameter setting */
- ldr r0, =S5P_PHYCONTROL0 @ 0xe6000018
- ldr r1, =0x50101000
- str r1, [r0]
+#endif
+#ifndef CONFIG_ONENAND_IPL
- ldr r0, =S5P_PHYCONTROL1 @ 0xe600001c
- ldr r1, =0xf4
- str r1, [r0]
please use the macro write8, write16 or write32 ans so on
- ldr r0, =S5P_PHYCONTROL2 @ 0xe6000020
- ldr r1, =0x0
- str r1, [r0]
- /* DLL on */
- ldr r0, =S5P_PHYCONTROL0 @ 0xe6000018
- ldr r1, =0x50101002
- str r1, [r0]
- /* DLL start */
- ldr r0, =S5P_PHYCONTROL0 @ 0xe6000018
- ldr r1, =0x50101003
- str r1, [r0]
- /* Force value locking for DLL off */
- ldr r0, =S5P_PHYCONTROL0 @ 0xe6000018
- ldr r1, =0x50101003
- str r1, [r0]
- /* DLL off */
- ldr r0, =S5P_PHYCONTROL0 @ 0xe6000018
- ldr r1, =0x50101001
- str r1, [r0]
- /* auto refresh off */
- ldr r0, =S5P_CONCONTROL @ 0xe6000000
- ldr r1, =0xff001010
- str r1, [r0]
+#endif
+#ifdef CONFIG_ONENAND_IPL
- /*
* BL%LE %LONG4, 2 chip, LPDDR, dynamic self refresh,* force precharge, dynamic power down off*/- ldr r0, =S5P_MEMCONTROL @ 0xe6000004
- ldr r1, =0x00212100
- str r1, [r0]
- /* 128MB config, 4banks */
- ldr r0, =S5P_MEMCONFIG0 @ 0xe6000008
- ldr r1, =0x20f80222
- str r1, [r0]
+#endif
+#ifndef CONFIG_ONENAND_IPL
- ldr r0, =S5P_MEMCONFIG1 @ 0xe600000c
- ldr r1, =0x28f80222
- str r1, [r0]
- ldr r0, =S5P_PRECHCONFIG @ 0xe6000014
- ldr r1, =0x20000000
- str r1, [r0]
+#endif
+#ifdef CONFIG_ONENAND_IPL
- /*
* 7.8us*166MHz%LE %LONG1294(0x50E) 7.8us*133MHz%LE %LONG1038(0x40E),* 100MHz%LE %LONG780(0x30C),* 20MHz%LE %LONG156(0x9C),* 10MHz%LE %LONG78(0x4E)*/- ldr r0, =S5P_TIMINGAREF @ 0xe6000030
- ldr r1, =0x0000050e
- str r1, [r0]
- /* 133MHz */
- ldr r0, =S5P_TIMINGROW @ 0xe6000034
- ldr r1, =0x0c233287
- str r1, [r0]
- /* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
- ldr r0, =S5P_TIMINGDATA @ 0xe6000038
- ldr r1, =0x32330303
- str r1, [r0]
- /* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
- ldr r0, =S5P_TIMINGPOWER @ 0xe600003c
- ldr r1, =0x04141433
- str r1, [r0]
- /* chip0 Deselect */
- ldr r0, =S5P_DIRECTCMD @ 0xe6000010
- ldr r1, =0x07000000
- str r1, [r0]
- /* chip0 PALL */
- ldr r0, =S5P_DIRECTCMD @ 0xe6000010
diff --git a/cpu/arm_cortexa8/s5pc100/interrupts.c
please rename it time.c
b/cpu/arm_cortexa8/s5pc100/interrupts.c new file mode 100644 index 0000000..3d2a2e5 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc100/interrupts.c @@ -0,0 +1,218 @@ +/*
- (C) Copyright 2003
- Texas Instruments <www.ti.com>
- (C) Copyright 2002
- Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- Marius Groeger mgroeger@sysgo.de
- (C) Copyright 2002
- Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- Alex Zuepke azu@sysgo.de
- (C) Copyright 2002-2004
- Gary Jennejohn, DENX Software Engineering, gj@denx.de
- (C) Copyright 2004
- Philippe Robin, ARM Ltd. philippe.robin@arm.com
- (C) Copyright 2008
- Guennadi Liakhovetki, DENX Software Engineering, lg@denx.de
are you sure that all this Copyright are needed?
- (C) Copyright 2009
- Heungjun Kim, SAMSUNG Electronics, riverful.kim@samsung.com
- Inki Dae, SAMSUNG Electronics, inki.dae@samsung.com
- Minkyu Kang, SAMSUNG Electronics, mk7.kang@samsung.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
diff --git a/cpu/arm_cortexa8/s5pc100/speed.c b/cpu/arm_cortexa8/s5pc100/speed.c new file mode 100644 index 0000000..9b5863b --- /dev/null +++ b/cpu/arm_cortexa8/s5pc100/speed.c @@ -0,0 +1,159 @@ +/*
- (C) Copyright 2001-2004
- Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- (C) Copyright 2002
- David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- (C) Copyright 2009
- Inki Dae, SAMSUNG Electronics, inki.dae@samsung.com
- Heungjun Kim, SAMSUNG Electronics, riverful.kim@samsung.com
- Minkyu Kang, SAMSUNG Electronics, mk7.kang@samsung.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+/*
- This code should work for both the S3C2400 and the S3C2410
- as they seem to have the same PLL and clock machinery inside.
- The different address mapping is handled by the s3c24xx.h files below.
- */
+#include <common.h> +#include <asm/arch/clock.h>
+#define APLL 0 +#define MPLL 1 +#define EPLL 2 +#define HPLL 3
+/* ------------------------------------------------------------------------- */ +/*
- NOTE: This describes the proper use of this file.
- CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- the specified bus in HZ.
- */
+/* ------------------------------------------------------------------------- */
+static unsigned long get_PLLCLK(int pllreg)
please use this scheme from clock rate function get_pll_clk_rate() get_xxx_clk_rate and please no upper case in function naming
+{
- unsigned long r, m, p, s, mask;
- switch (pllreg) {
- case APLL:
r = S5P_APLL_CON_REG;break;- case MPLL:
+/* return UCLK frequency */ +unsigned long get_UCLK(void) +{
- return get_PLLCLK(EPLL);
+}
please add #idef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void) +{
- printf("CPU:\tS5PC100@%luMHz\n", get_ARMCLK() / 1000000);
- printf("\tFclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz\n",
get_FCLK() / 1000000, get_HCLK() / 1000000,get_PCLK() / 1000000);
please use strmhz
Best Regards, J.