This patch adds general board files based on MT7987 SoC.
MT7987 uses one mmc controller for booting from both SD and eMMC, and the pins of mmc controller are also shared with one spi controller. So three configs are need for these boot types:
1. mt7987_rfb_defconfig - SPI-NOR (spi2) and SPI-NAND (spi0) 2. mt7987_emmc_rfb_defconfig - eMMC + SPI-NOR (spi2) 3. mt7987_sd_rfb_defconfig - SD + SPI-NOR (spi2)
Note: spi2 also supports booting from SPI-NAND, but not the default option.
Signed-off-by: Sam Shih sam.shih@mediatek.com Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi | 61 +++++++++++++++ arch/arm/dts/mt7987a-emmc-rfb.dts | 37 +++++++++ arch/arm/dts/mt7987a-rfb-u-boot.dtsi | 71 ++++++++++++++++++ arch/arm/dts/mt7987a-rfb.dts | 34 +++++++++ arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi | 59 +++++++++++++++ arch/arm/dts/mt7987a-sd-rfb.dts | 37 +++++++++ board/mediatek/mt7987/MAINTAINERS | 8 ++ board/mediatek/mt7987/Makefile | 3 + board/mediatek/mt7987/mt7987_rfb.c | 10 +++ configs/mt7987_emmc_rfb_defconfig | 91 +++++++++++++++++++++++ configs/mt7987_rfb_defconfig | 87 ++++++++++++++++++++++ configs/mt7987_sd_rfb_defconfig | 91 +++++++++++++++++++++++ include/configs/mt7987.h | 14 ++++ 13 files changed, 603 insertions(+) create mode 100644 arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi create mode 100644 arch/arm/dts/mt7987a-emmc-rfb.dts create mode 100644 arch/arm/dts/mt7987a-rfb-u-boot.dtsi create mode 100644 arch/arm/dts/mt7987a-rfb.dts create mode 100644 arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi create mode 100644 arch/arm/dts/mt7987a-sd-rfb.dts create mode 100644 board/mediatek/mt7987/MAINTAINERS create mode 100644 board/mediatek/mt7987/Makefile create mode 100644 board/mediatek/mt7987/mt7987_rfb.c create mode 100644 configs/mt7987_emmc_rfb_defconfig create mode 100644 configs/mt7987_rfb_defconfig create mode 100644 configs/mt7987_sd_rfb_defconfig create mode 100644 include/configs/mt7987.h
diff --git a/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi new file mode 100644 index 00000000000..54cf72b3bf8 --- /dev/null +++ b/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "mt7987a-u-boot.dtsi" +#include "mt7987-netsys-u-boot.dtsi" + +/ { + model = "mt7987"; + compatible = "mediatek,mt7987", "mediatek,mt7987-emmc-rfb"; +}; + +ð0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins>; + phy-mode = "2500base-x"; + mediatek,switch = "auto"; + reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pins_default>; + max-frequency = <48000000>; + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + /delete-node/ spi_nor@0; + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; diff --git a/arch/arm/dts/mt7987a-emmc-rfb.dts b/arch/arm/dts/mt7987a-emmc-rfb.dts new file mode 100644 index 00000000000..f59e5bd97bf --- /dev/null +++ b/arch/arm/dts/mt7987a-emmc-rfb.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include "mt7987a.dtsi" +#include "mt7987-emmc.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "MediaTek MT7987 EMMC RFB"; + compatible = "mediatek,mt7987a-emmc", + "mediatek,mt7987a", "mediatek,mt7987"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11000000 \ + pci=pcie_bus_perf ubi.block=0,firmware \ + root=/dev/fit0 rootwait"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + + wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + }; +}; diff --git a/arch/arm/dts/mt7987a-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-rfb-u-boot.dtsi new file mode 100644 index 00000000000..f1ed51e21c4 --- /dev/null +++ b/arch/arm/dts/mt7987a-rfb-u-boot.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Sam Shih sam.shih@mediatek.com + */ + +#include "mt7987a-u-boot.dtsi" +#include "mt7987-netsys-u-boot.dtsi" + +ð0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins>; + phy-mode = "2500base-x"; + mediatek,switch = "auto"; + reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + /delete-node/ spi_nand@0; + spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + /delete-node/ spi_nor@0; + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; diff --git a/arch/arm/dts/mt7987a-rfb.dts b/arch/arm/dts/mt7987a-rfb.dts new file mode 100644 index 00000000000..0ba6b8d9ad7 --- /dev/null +++ b/arch/arm/dts/mt7987a-rfb.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include "mt7987a.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "MediaTek MT7987A RFB"; + compatible = "mediatek,mt7987a", "mediatek,mt7987"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11000000 \ + pci=pcie_bus_perf"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + + wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + }; +}; diff --git a/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi new file mode 100644 index 00000000000..b07e6da41e2 --- /dev/null +++ b/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "mt7987a-u-boot.dtsi" +#include "mt7987-netsys-u-boot.dtsi" + +/ { + model = "mt7987"; + compatible = "mediatek,mt7987", "mediatek,mt7987-sd-rfb"; +}; + +ð0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins>; + phy-mode = "2500base-x"; + mediatek,switch = "auto"; + reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&sd_pins_default>; + max-frequency = <48000000>; + bus-width = <4>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + /delete-node/ spi_nor@0; + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; diff --git a/arch/arm/dts/mt7987a-sd-rfb.dts b/arch/arm/dts/mt7987a-sd-rfb.dts new file mode 100644 index 00000000000..85de4990682 --- /dev/null +++ b/arch/arm/dts/mt7987a-sd-rfb.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include "mt7987a.dtsi" +#include "mt7987-sd.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "MediaTek MT7987 SD RFB"; + compatible = "mediatek,mt7987a-sd", + "mediatek,mt7987a", "mediatek,mt7987"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11000000 \ + pci=pcie_bus_perf ubi.block=0,firmware \ + root=/dev/fit0 rootwait"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + + wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + }; +}; diff --git a/board/mediatek/mt7987/MAINTAINERS b/board/mediatek/mt7987/MAINTAINERS new file mode 100644 index 00000000000..c257d0b09df --- /dev/null +++ b/board/mediatek/mt7987/MAINTAINERS @@ -0,0 +1,8 @@ +MT7987 +M: Sam Shih sam.shih@mediatek.com +S: Maintained +F: board/mediatek/mt7987 +F: include/configs/mt7987.h +F: configs/mt7987_rfb_defconfig +F: configs/mt7987_emmc_rfb_defconfig +F: configs/mt7987_sd_rfb_defconfig diff --git a/board/mediatek/mt7987/Makefile b/board/mediatek/mt7987/Makefile new file mode 100644 index 00000000000..9f3f493f3c9 --- /dev/null +++ b/board/mediatek/mt7987/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += mt7987_rfb.o diff --git a/board/mediatek/mt7987/mt7987_rfb.c b/board/mediatek/mt7987/mt7987_rfb.c new file mode 100644 index 00000000000..fcb844deed8 --- /dev/null +++ b/board/mediatek/mt7987/mt7987_rfb.c @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam Shih sam.shih@mediatek.com + */ + +int board_init(void) +{ + return 0; +} diff --git a/configs/mt7987_emmc_rfb_defconfig b/configs/mt7987_emmc_rfb_defconfig new file mode 100644 index 00000000000..022ca32169b --- /dev/null +++ b/configs/mt7987_emmc_rfb_defconfig @@ -0,0 +1,91 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7987a-emmc-rfb" +CONFIG_TARGET_MT7987=y +CONFIG_SYS_BOOTM_LEN=0x6000000 +CONFIG_SYS_LOAD_ADDR=0x48000000 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_DEBUG_UART=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +# CONFIG_AUTOBOOT is not set +CONFIG_DEFAULT_FDT_FILE="mt7987a-emmc-rfb" +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 +CONFIG_LOG=y +CONFIG_SYS_PROMPT="MT7987> " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_PWM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PING=y +CONFIG_CMD_SMC=y +CONFIG_EFI_PARTITION=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.2" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_PUYA=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI=y +CONFIG_PHY_ETHERNET_ID=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7987=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_DM_PWM=y +CONFIG_PWM_MTK=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y +CONFIG_HEXDUMP=y diff --git a/configs/mt7987_rfb_defconfig b/configs/mt7987_rfb_defconfig new file mode 100644 index 00000000000..00e3cea5264 --- /dev/null +++ b/configs/mt7987_rfb_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7987a-rfb" +CONFIG_TARGET_MT7987=y +CONFIG_SYS_BOOTM_LEN=0x6000000 +CONFIG_SYS_LOAD_ADDR=0x48000000 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_DEBUG_UART=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +# CONFIG_AUTOBOOT is not set +CONFIG_DEFAULT_FDT_FILE="mt7987a-rfb" +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 +CONFIG_LOG=y +CONFIG_SYS_PROMPT="MT7987> " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_PWM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PING=y +CONFIG_CMD_SMC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.2" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_PUYA=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI=y +CONFIG_PHY_ETHERNET_ID=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7987=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_DM_PWM=y +CONFIG_PWM_MTK=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y +CONFIG_HEXDUMP=y diff --git a/configs/mt7987_sd_rfb_defconfig b/configs/mt7987_sd_rfb_defconfig new file mode 100644 index 00000000000..ca7714b1242 --- /dev/null +++ b/configs/mt7987_sd_rfb_defconfig @@ -0,0 +1,91 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7987a-sd-rfb" +CONFIG_TARGET_MT7987=y +CONFIG_SYS_BOOTM_LEN=0x6000000 +CONFIG_SYS_LOAD_ADDR=0x48000000 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_DEBUG_UART=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +# CONFIG_AUTOBOOT is not set +CONFIG_DEFAULT_FDT_FILE="mt7987a-sd-rfb" +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 +CONFIG_LOG=y +CONFIG_SYS_PROMPT="MT7987> " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_PWM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PING=y +CONFIG_CMD_SMC=y +CONFIG_EFI_PARTITION=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.2" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_PUYA=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI=y +CONFIG_PHY_ETHERNET_ID=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7987=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_DM_PWM=y +CONFIG_PWM_MTK=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y +CONFIG_HEXDUMP=y diff --git a/include/configs/mt7987.h b/include/configs/mt7987.h new file mode 100644 index 00000000000..18ed3c7a55b --- /dev/null +++ b/include/configs/mt7987.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for MediaTek MT7987 SoC + * + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam Shih sam.shih@mediatek.com + */ + +#ifndef __MT7987_H +#define __MT7987_H + +#define CFG_MAX_MEM_MAPPED 0xC0000000 + +#endif