Thanks Jagan,
-----Original Message----- From: Jagan Teki [mailto:jteki@openedev.com] Sent: Wednesday, September 23, 2015 4:00 AM To: Vikas MANOCHA Cc: u-boot@lists.denx.de; Stefan Roese; Graham Moore; Marek VaĊĦut Subject: Re: [U-Boot] [PATCH v6 5/5] spi: cadence_qspi: get fifo width from device tree
Hi Vikas,
On 11 September 2015 at 23:58, Vikas Manocha vikas.manocha@st.com wrote:
Fifo width could be different on different socs, e.g. stv0991 & altera soc have different fifo width.
Signed-off-by: Vikas Manocha vikas.manocha@st.com
Reviewed-by: Jagan Teki jteki@openedev.com
Changes in v6: none Changes in v5: none Changes in v4: alligned to linux device tree binding. Changes in v3: none Changes in v2: Rebased to master
arch/arm/dts/socfpga.dtsi | 1 + arch/arm/dts/stv0991.dts | 1 + drivers/spi/cadence_qspi.c | 1 + drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 24 ++++++++++-------------- 5 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 9756544..5f0b0fa 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -640,6 +640,7 @@ num-cs = <4>; fifo-depth = <128>; cdns,trigger-address = <0x00000000>;
cdns,fifo-width = <4>; sram-size = <128>; bus-num = <2>; status = "disabled"; diff --gita/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts index 6bc5372..0a88b69 100644 --- a/arch/arm/dts/stv0991.dts +++ b/arch/arm/dts/stv0991.dts @@ -34,6 +34,7 @@ clocks = <3750000>; sram-size = <256>; cdns,trigger-address = <0x40000000>;
cdns,fifo-width = <8>; status = "okay"; flash0: n25q32@0 { diff --gita/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index c63f583..0430218 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -312,6 +312,7 @@ static int cadence_spi_ofdata_to_platdata(struct
udevice *bus)
plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20); plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); plat->sram_size = fdtdec_get_int(blob, node, "sram-size",128);
plat->fifo_width = fdtdec_get_int(blob, node,"cdns,fifo-width", 4);
debug("%s: regbase=%p flashbase=%p trigger_base=%p max-frequency=%d page-size=%d\n",
__func__, plat->regbase, plat->flashbase,plat->trigger_base, diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 7341339..91f38f1 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -27,6 +27,7 @@ struct cadence_spi_platdata { u32 tchsh_ns; u32 tslch_ns; u32 sram_size;
u32 fifo_width;};
struct cadence_spi_priv { diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 2638f00..478b5a0 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -34,8 +34,6 @@ #define CQSPI_REG_RETRY (10000) #define CQSPI_POLL_IDLE_RETRY (3)
-#define CQSPI_FIFO_WIDTH (4)
#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
/* Transfer mode */ @@ -48,9 +46,6 @@ #define CQSPI_DUMMY_CLKS_PER_BYTE (8) #define CQSPI_DUMMY_BYTES_MAX (4)
-#define CQSPI_REG_SRAM_FILL_THRESHOLD \
This removal is out-of-scope wrt this patch, create one more patch for this.
Agreed, I will create another patch in next version.
Rgds, Vikas
((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)/**********************************************************
- Controller's configuration and status register (offset from QSPI_BASE)
******/ @@ -214,7 +209,7 @@ static void cadence_qspi_apb_read_fifo_data(void *dest, }
static void cadence_qspi_apb_write_fifo_data(const void
*dest_ahb_addr,
const void *src, unsigned int bytes)
const void *src, unsigned int fifo_width, unsigned int bytes){ unsigned int temp = 0; int i; @@ -222,11 +217,11 @@ static void
cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr; unsigned int *src_ptr = (unsigned int *)src;
while (remaining >= CQSPI_FIFO_WIDTH) {for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i >= 0; i--)
while (remaining >= fifo_width) {for (i = fifo_width/sizeof(src_ptr) - 1; i >= 0; i--) writel(*(src_ptr+i), dest_ptr+i);
src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr);remaining -= CQSPI_FIFO_WIDTH;
src_ptr += fifo_width/sizeof(src_ptr);remaining -= fifo_width; } if (remaining) { /* dangling bytes */@@ -241,7 +236,7 @@ static void
cadence_qspi_apb_write_fifo_data(const
void *dest_ahb_addr,
/* Read from SRAM FIFO with polling SRAM fill level. */ static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
const void *src_addr, unsigned int num_bytes)
const void *src_addr, unsigned int fifo_width, unsigned int- num_bytes)
{ unsigned int remaining = num_bytes; unsigned int retry; @@ -263,7 +258,7 @@ static int qspi_read_sram_fifo_poll(const void
*reg_base, void *dest_addr,
return -1; }
sram_level *= CQSPI_FIFO_WIDTH;
sram_level *= fifo_width; sram_level = sram_level > remaining ? remaining :sram_level;
/* Read data from FIFO. */ @@ -305,7 +300,8 @@ staticint qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat, wr_bytes = (remaining > page_size) ? page_size : remaining;
cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes);
cadence_qspi_apb_write_fifo_data(dest_addr, src,plat->fifo_width,- wr_bytes); src += wr_bytes; remaining -= wr_bytes; }
@@ -752,7 +748,7 @@ int
cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
plat->regbase + CQSPI_REG_INDIRECTRD); if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf,
(const void *)plat->trigger_base, rxlen))
(const void *)plat->trigger_base, plat->fifo_width,rxlen)) goto failrd;
/* Check flash indirect controller */-- 1.7.9.5
-- Jagan | openedev.