
12 Jul
2021
12 Jul
'21
1:24 p.m.
st 7. 7. 2021 v 8:45 odesÃlatel Michal Simek michal.simek@xilinx.com napsal:
lpd_lsbus is clock which is used by many IPs like dmas, gems, gpio, sdhcis, spis, ttcs, uarts, watchdog that's why make sense to also enable access to change this clock. For this clock you already get the rate.
Signed-off-by: Michal Simek michal.simek@xilinx.com
drivers/clk/clk_zynqmp.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 13a623fdb96a..52fecec7a7a9 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -813,6 +813,7 @@ static int zynqmp_clk_enable(struct clk *clk) mask = 0x3; break; case qspi_ref ... can1_ref:
case lpd_lsbus: clkact_shift = 24; mask = 0x1; break;
-- 2.32.0
Applied. M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs