-----Original Message----- From: Marek Vasut marex@denx.de Sent: Tuesday, 14 September, 2021 11:26 AM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com Subject: [PATCH 6/8] arm: socfpga: vining: Fix UDC controller phandle in DT
The USB peripheral controller is the DWC2 controller 1, not 0. Update the phandle to fix UDC support on this board.
Signed-off-by: Marek Vasut marex@denx.de Cc: Siew Chin Lim elly.siew.chin.lim@intel.com Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Cc: Tien Fong Chee tien.fong.chee@intel.com
arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Tien Fong Chee tien.fong.chee@intel.com
Regards, TF