Sync the code from puma-rk3399: 8adc9d1 rockchip: board: puma_rk3399: derive ethaddr from cpuid 9415b9a rockchip: board: puma_rk3399: add support for serial# and cpuid# via efuses
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
board/rockchip/evb_rk3399/evb-rk3399.c | 123 ++++++++++++++++++++++++++++++++- 1 file changed, 121 insertions(+), 2 deletions(-)
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index d50c59d..40fc1a5 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -5,23 +5,29 @@ */ #include <common.h> #include <dm.h> +#include <misc.h> #include <ram.h> #include <dm/pinctrl.h> #include <dm/uclass-internal.h> +#include <asm/setup.h> #include <asm/arch/periph.h> #include <power/regulator.h> +#include <u-boot/sha256.h>
DECLARE_GLOBAL_DATA_PTR;
+#define RK3399_CPUID_OFF 0x7 +#define RK3399_CPUID_LEN 0x10 + int board_init(void) { struct udevice *pinctrl, *regulator; int ret;
/* - * The PWM do not have decicated interrupt number in dts and can + * The PWM does not have decicated interrupt number in dts and can * not get periph_id by pinctrl framework, so let's init them here. - * The PWM2 and PWM3 are for pwm regulater. + * The PWM2 and PWM3 are for pwm regulators. */ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { @@ -67,3 +73,116 @@ int board_init(void) out: return 0; } + +static void setup_macaddr(void) +{ +#if CONFIG_IS_ENABLED(CMD_NET) + int ret; + const char *cpuid = getenv("cpuid#"); + u8 hash[SHA256_SUM_LEN]; + int size = sizeof(hash); + u8 mac_addr[6]; + + /* Only generate a MAC address, if none is set in the environment */ + if (getenv("ethaddr")) + return; + + if (!cpuid) { + debug("%s: could not retrieve 'cpuid#'\n", __func__); + return; + } + + ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); + if (ret) { + debug("%s: failed to calculate SHA256\n", __func__); + return; + } + + /* Copy 6 bytes of the hash to base the MAC address on */ + memcpy(mac_addr, hash, 6); + + /* Make this a valid MAC address and set it */ + mac_addr[0] &= 0xfe; /* clear multicast bit */ + mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ + eth_setenv_enetaddr("ethaddr", mac_addr); +#endif + + return; +} + +static void setup_serial(void) +{ +#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) + struct udevice *dev; + int ret, i; + u8 cpuid[RK3399_CPUID_LEN]; + u8 low[RK3399_CPUID_LEN/2], high[RK3399_CPUID_LEN/2]; + char cpuid_str[RK3399_CPUID_LEN * 2 + 1]; + u64 serialno; + char serialno_str[16]; + + /* retrieve the device */ + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(rockchip_efuse), &dev); + if (ret) { + debug("%s: could not find efuse device\n", __func__); + return; + } + + /* read the cpu_id range from the efuses */ + ret = misc_read(dev, RK3399_CPUID_OFF, &cpuid, sizeof(cpuid)); + if (ret) { + debug("%s: reading cpuid from the efuses failed\n", + __func__); + return; + } + + memset(cpuid_str, 0, sizeof(cpuid_str)); + for (i = 0; i < 16; i++) + sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); + + debug("cpuid: %s\n", cpuid_str); + + /* + * Mix the cpuid bytes using the same rules as in + * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c + */ + for (i = 0; i < 8; i++) { + low[i] = cpuid[1 + (i << 1)]; + high[i] = cpuid[i << 1]; + } + + serialno = crc32_no_comp(0, low, 8); + serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; + snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); + + setenv("cpuid#", cpuid_str); + setenv("serial#", serialno_str); +#endif + + return; +} + +int misc_init_r(void) +{ + setup_serial(); + setup_macaddr(); + + return 0; +} + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *serial_string; + u64 serial = 0; + + serial_string = getenv("serial#"); + + if (serial_string) + serial = simple_strtoull(serial_string, NULL, 16); + + serialnr->high = (u32)(serial >> 32); + serialnr->low = (u32)(serial & 0xffffffff); +} +#endif