On Sun, Oct 12, 2014 at 04:23:05PM +0800, Chen-Yu Tsai wrote:
On Sun, Oct 12, 2014 at 12:05 AM, Ian Campbell ijc@hellion.org.uk wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
From: Hans de Goede hdegoede@redhat.com
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond.
Does it also have enough space for 9 banks? Since you overlay a struct sunxi_gpio_reg on it which has a gpio_bank[SUNXI_GPIO_BANKS] over it.
Yes it does, as seen in the latest A31 manuals released by Allwinner.
SUNXI_GPIO_BANKS is now also confusingly named since it is really "number of banks on the first/original GPIO controller". Eventually someone will use it as the actual total and be very sad.
I think it might be best if we retcon some distinct name onto the original GPIO controller so we can have SUNXIO_GPIO_BLA_BANKS and SUNXI_GPIO_R_BANKS (or even just call them controller 0 and 1 and have SUNXI_GPIO0_BANKS and SUNXI_GPIO1_BANKS, if that's not too confusing)
The latest manuals have "CPUx-PORT" and "CPUs-PORT" for the respective chapters. I'm guessing "x" is for 0~3 cores, and s is for standby or something.
iirc, it was meant for "special".
Of course it's also confusing that Allwinner's sources use the "R_" prefix for all hardware in that address range, while the datasheet lists the GPIO function names as "s_something".
We use the same pin convention than in the datasheet in mainline (but starting from PL for the special pins). And it's true that we do prefix all the functions by s_, once again, just like the datasheet does.
The fact that it comes from a different controller is only expressed by where the pinctrl pins node is defined in the DT.
Maxime