This patchset allows us runing u-boot in S-mode which is useful on platforms where M-mode runtime firmware is an independent firmware and u-boot is used as last stage OS bootloader.
The patchset based upon git://git.denx.de/u-boot-riscv.git and is tested on QEMU in both M-mode and S-mode.
For S-mode testing, we have used u-boot.bin as payload of latest BBL (at commit 6ebd0f2a46255d0c76dad3c05b16c1d154795d26) applied with following changes:
diff --git a/machine/emulation.c b/machine/emulation.c index 132e977..def75e1 100644 --- a/machine/emulation.c +++ b/machine/emulation.c @@ -162,6 +162,12 @@ static inline int emulate_read_csr(int num, uintptr_t mstatus, uintptr_t* result
switch (num) { + case CSR_MISA: + *result = read_csr(misa); + return 0; + case CSR_MHARTID: + *result = read_csr(mhartid); + return 0; case CSR_CYCLE: if (!((counteren >> (CSR_CYCLE - CSR_CYCLE)) & 1)) return -1;
Changes since v6: - Added patch for S-mode timer implementation
Changes since v5: - Dropped PATCH4 to remove redundant a2 store on DRAM base in start.S because it will taken care by Rick as separate patch - Added MODE_PREFIX() macro to generate mode specific CSR names
Changes since v4: - Rebased series based on commit 52923c6db7f00e0197ec894c8c1bb8a7681974bb of git://git.denx.de/u-boot-riscv.git - Added a patch to remove redundant a2 store on DRAM base. This store was creating problem booting U-Boot in S-mode using BBL.
Changes since v3: - Replaced 'u-boot' with 'U-Boot' in commit message - Dropped 'an' in RISCV_SMODE kconfig option help message - Added appropriate #ifdef in arch/riscv/lib/interrupts.c
Changes since v2: - Dropped 'default n" from RISCV_SMODE kconfig option - Replaced '-smode_' in defconfig names with '_smode_'
Changes since v1: - Rebased upon latest git://git.denx.de/u-boot-riscv.git - Add details in cover letter for running u-boot in S-mode using BBL
Anup Patel (4): riscv: Add kconfig option to run U-Boot in S-mode riscv: qemu: Use different SYS_TEXT_BASE for S-mode riscv: Add S-mode defconfigs for QEMU virt machine RISC-V: Add S-mode timer implementation
arch/Kconfig | 1 - arch/riscv/Kconfig | 17 ++++++++ arch/riscv/cpu/start.S | 23 ++++++---- arch/riscv/include/asm/encoding.h | 6 +++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/interrupts.c | 31 +++++++++---- arch/riscv/lib/time.c | 60 ++++++++++++++++++++++++++ board/emulation/qemu-riscv/Kconfig | 3 +- board/emulation/qemu-riscv/MAINTAINERS | 2 + configs/qemu-riscv32_smode_defconfig | 10 +++++ configs/qemu-riscv64_smode_defconfig | 11 +++++ 11 files changed, 146 insertions(+), 19 deletions(-) create mode 100644 arch/riscv/lib/time.c create mode 100644 configs/qemu-riscv32_smode_defconfig create mode 100644 configs/qemu-riscv64_smode_defconfig