
2 Aug
2015
2 Aug
'15
11:17 a.m.
On 20/07/2015 13:28, Peng Fan wrote:
i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6 chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled. There is on specific switch for on/off L2 Cache, so default select SYS_L2CACHE_OFF.
Signed-off-by: Peng Fan Peng.Fan@freescale.com
Changes v3: none
Changes v2: refine commit msg.
arch/arm/cpu/armv7/mx6/Kconfig | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 10908c4..fceba27 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -25,6 +25,10 @@ config MX6SL config MX6SX bool
+config MX6UL
- select SYS_L2CACHE_OFF
- bool
choice prompt "MX6 board select" optional
Applied to u-boot-imx, thanks !
Best regards, Stefano Babic
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