Re: [PATCH 1/1] riscv: define a cache line size for QEMU

On Fri, Jul 21, 2023 at 8:59 PM Heinrich Schuchardt heinrich.schuchardt@canonical.com wrote:

The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set.

Define the cache line size for QEMU on RISC-V to be 64 bytes.

Signed-off-by: Heinrich Schuchardt heinrich.schuchardt@canonical.com

arch/Kconfig | 1 + arch/riscv/Kconfig | 1 + 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 867cbcbe74..be6a956bb9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -16,6 +16,7 @@ config TARGET_MICROCHIP_ICICLE

config TARGET_QEMU_VIRT bool "Support QEMU Virt Board"

•   select SYS_CACHE_SHIFT_6
  
  

config TARGET_SIFIVE_UNLEASHED bool "Support SiFive Unleashed Board" --

I'd prefer we put this under GENERIC_RISCV as cache is determined by CPU, not by board.

Regards, Bin