ping?
On Tue, Jun 23, 2009 at 05:30:05PM +0200, Daniel Mack wrote:
From: Daniel Mack daniel@caiaq.de To: u-boot@lists.denx.de Cc: Daniel Mack daniel@caiaq.de Subject: [PATCH 2/2] pxa: fix CKEN_B register bits Date: Tue, 23 Jun 2009 17:30:05 +0200 Message-Id: 1245771005-23299-2-git-send-email-daniel@caiaq.de X-Mailer: git-send-email 1.6.3.1
The current defition for CKEN_B register bits is nonsense. Adding 32 to the shifted value is equal to '| (1 << 5)', and this bit is marked 'reserved' in the PXA docs.
Signed-off-by: Daniel Mack daniel@caiaq.de
include/asm-arm/arch-pxa/pxa-regs.h | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 1f81e11..2a723dc 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1953,12 +1953,12 @@ typedef void (*ExcpHndlr) (void) ; #define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */
#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */ -#define CKENB_8_1WIRE ((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */ -#define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */ -#define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */ -#define CKENB_4_I2C ((1 << 4) + 32) /* I2C Unit Clock Enable */ -#define CKENB_1_PWM1 ((1 << 1) + 32) /* PWM2 & PWM3 Clock Enable */ -#define CKENB_0_PWM0 ((1 << 0) + 32) /* PWM0 & PWM1 Clock Enable */ +#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */ +#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */ +#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */ +#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */ +#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */ +#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */
#else /* if defined CONFIG_CPU_MONAHANS */
-- 1.6.3.1