LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3 and shared same stream-id partitioning. This patch rewords the definition to support all these SOCs.
Signed-off-by: Bharat Bhushan Bharat.Bhushan@nxp.com --- arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index ee28323..6e97909 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -8,11 +8,11 @@ #define __FSL_STREAM_ID_H
/* - * Stream IDs on ls2080a devices are not hardwired and are - * programmed by sw. There are a limited number of stream IDs - * available, and the partitioning of them is scenario dependent. - * This header defines the partitioning between legacy, PCI, - * and DPAA2 devices. + * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a) + * devices are not hardwired and are programmed by sw. There are a limited + * number of stream IDs available, and the partitioning of them is scenario + * dependent. This header defines the partitioning between legacy, + * PCI, and DPAA2 devices. * * This partitioning can be customized in this file depending * on the specific hardware config: @@ -36,7 +36,7 @@ * -the MC is responsible for allocating and setting up 'isolation context * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. * - * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for + * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for * each of the different bus masters. The relationship between * the AMQ registers and stream IDs is defined in the table below: * AMQ bit streamID bit