Hi Saket,
On Thu, Jun 4, 2015 at 11:23 AM, Simon Glass sjg@chromium.org wrote:
Hi John,
On 3 June 2015 at 18:13, Bin Meng bmeng.cn@gmail.com wrote:
Hi,
On Thu, Jun 4, 2015 at 5:44 AM, John Hawley john.hawley@intel.com wrote:
Ok some more data points. I tested with the FSP3 Gold that Saket built, and it continues to work on the A0, but it continues to not work on the A2 D0 board I have. I'm guessing this is something between the steppings in the CPU and the FSP, but I'm not sure.
Adding Vincent to this, as I'm guessing there is something going on here with the interaction with the FSP (since it works on an A0 B3, but not an A2 D0)
- John
On 06/03/2015 01:24 PM, Saket Sinha wrote:
Hi,
I'm 99% sure that's the issue. try with FSP 3 gold."
I am now trying to build the u-boot.rom from FSP 3 gold and would let you know about the results ASAP.
u-boot.rom prepared from FSP3-Gold dowmloaded from https://downloadcenter.intel.com/download/24496 doesn't work with the minnowmax I have.
Regards, Saket Sinha
Given even with Simon's debug UART WIP patch, the A2 D0 board still has nothing output, I suspect that the FspTempRamInit() call failed due to the microcode loading. Could it be the problem that the microcode passed to the FSP is a little bit old that it does not support the D0 stepping. Can you try some newer version microcode to see if there is any luck?
I was using the Gold3 version. Is there a new microcode we could try?
I've created two patches to include a D0 stepping microcode for BayTrail-I. The microcode was generated from the microcode header in the coreboot source tree.
The first patch is waiting for the list moderator's approval as it exceeds the mailing list size. The second patch is at http://patchwork.ozlabs.org/patch/480673/ I will send the first patch to you offline. Please have a try.
Regards, Bin