Hi Fabio,
On 03.07.21 21:58, Fabio Estevam wrote:
From: Frieder Schrempf frieder.schrempf@kontron.de
Currently we can't use DM_USB in SPL as the ci_udc driver is not ported to DM yet.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Signed-off-by: Fabio Estevam festevam@denx.de
arch/arm/include/asm/arch-imx8m/clock.h | 1 + arch/arm/mach-imx/imx8m/clock_imx8mm.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h index 77d9428a188a..fcd111c918fd 100644 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -276,3 +276,4 @@ int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); int set_clk_enet(enum enet_freq type); int set_clk_eqos(enum enet_freq type); void hab_caam_clock_enable(unsigned char enable); +void enable_usboh3_clk(unsigned char enable); diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index f8e4ec0d9052..dd40e2f1e772 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -277,6 +277,22 @@ int intpll_configure(enum pll_clocks pll, ulong freq) return 0; }
+void enable_usboh3_clk(unsigned char enable) +{
- if (enable) {
clock_enable(CCGR_USB_MSCALE_PL301, 0);/* 500M */clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));/* 100M */clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));/* 100M */clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));clock_enable(CCGR_USB_MSCALE_PL301, 1);- } else {
clock_enable(CCGR_USB_MSCALE_PL301, 0);- }
+}
- void init_uart_clk(u32 index) { /*
This breaks phycore-imx8mp, I cannot build it anymore. Could you take a look ?
Best regards, Stefano