On 23 May 2016 at 01:08, Mario Six mario.six@gdsys.cc wrote:
From: "mario.six@gdsys.cc" mario.six@gdsys.cc
This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well).
Each GPIO bank is identified by its own entry in the device tree, i.e.
gpio-controller@fc00 { #gpio-cells = <2>; compatible = "fsl,pq3-gpio"; reg = <0xfc00 0x100> }
By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC).
The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported.
The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well.
Signed-off-by: Mario Six mario.six@gdsys.cc
v4: None
v3:
- Added shadow for the GPDAT register, as suggested by Joakim Tjernlund
- Switched to u32 for bit masks
- Added some comments
v2:
- Added missing commit message
- Improved the Kconfig description
- Fixed and documented the mpc85xx_gpio_data members
- Introduced GPIO_MASK macro to simplify the code
- Fixed white space issues in function headers
- Removed unnecessary empty line
- Use fdtdec_get_addr_size_auto_noparent to read the register base data
arch/powerpc/include/asm/arch-mpc85xx/gpio.h | 2 + arch/powerpc/include/asm/immap_85xx.h | 2 + drivers/gpio/Kconfig | 25 ++++ drivers/gpio/Makefile | 1 + drivers/gpio/mpc85xx_gpio.c | 187 +++++++++++++++++++++++++++ 5 files changed, 217 insertions(+) create mode 100644 drivers/gpio/mpc85xx_gpio.c
Reviewed-by: Simon Glass sjg@chromium.org