MPC8379E RM says (10-34): Once LCRR[CLKDIV] is written, the register should be read, and then an isync should be executed. So update this in code. Also define a LCRR mask for processors, which uses not all bits in the LCRR register (as for example mpc832x did).
Signed-off-by: Heiko Schocher hs@denx.de --- cpu/mpc83xx/cpu_init.c | 11 +++++++++-- include/mpc83xx.h | 5 +++++ 2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index ea4f2af..b733fce 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -23,8 +23,8 @@ #include <common.h> #include <mpc83xx.h> #include <ioports.h> -#ifdef CONFIG_USB_EHCI_FSL #include <asm/io.h> +#ifdef CONFIG_USB_EHCI_FSL #include <usb/ehci-fsl.h> #endif
@@ -194,7 +194,14 @@ void cpu_init_f (volatile immap_t * im) im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
/* LCRR - Clock Ratio Register (10.3.1.16) */ - im->lbus.lcrr = CONFIG_SYS_LCRR; + out_be32(&im->lbus.lcrr, ((in_be32(&im->lbus.lcrr) & ~LCRR_MASK) | \ + (CONFIG_SYS_LCRR & LCRR_MASK))); + /* MPC8379E RM 10-34 says after writting this register + * the register should be reread and an isync should be + * executed. + */ + in_be32(&im->lbus.lcrr); + isync();
/* Enable Time Base & Decrimenter ( so we will have udelay() )*/ im->sysconf.spcr |= SPCR_TBEN; diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 44115c9..41bb845 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -198,6 +198,7 @@ #define SICRL_URT_CTPR 0x06000000 #define SICRL_IRQ_CTPR 0x00C00000
+#define LCRR_MASK 0x0003000f #elif defined(CONFIG_MPC8313) /* SICRL bits - MPC8313 specific */ #define SICRL_LBC 0x30000000 @@ -1200,6 +1201,10 @@
#define PEX_GCLK_RATIO 0x440
+#if !defined(LCRR_MASK) +#define LCRR_MASK 0xFFFFFFFF +#endif + #ifndef __ASSEMBLY__ struct pci_region; void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);