The rk3318 A95X Z2 boards are sold as TV box. No further documentation is given, but from the dts files extracted it seems that the rk3318 processor is simulair to the rk3328. Included is an extra dtsi file for U-Boot specific properties. The DT is already located in the /dts/upstream directory.
Features:
CPU: RK3318 Quad-Core Cortex-A53 GPU: Mali-450 RAM: 2/4GB DDR3 ROM: EMMC 16/32/64GB HDMI: HDMI 2.0a for 4k@60Hz Ethernet: 10/100M standard RJ-45 WiFi: 2.4G+5G WIFI, 802.11 b/g/n Bluetooth: 4.0 1 x USB 3.0 1 x USB 2.0 1 x Micro SD card slot 1 x SPDIF 1 x AV 1 x DC IN
Signed-off-by: Johan Jonker jbx6244@gmail.com --- arch/arm/dts/rk3318-a95x-z2-u-boot.dtsi | 9 +++ board/rockchip/evb_rk3328/MAINTAINERS | 6 ++ configs/a95x-z2-rk3318_defconfig | 94 +++++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 4 +- 4 files changed, 112 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3318-a95x-z2-u-boot.dtsi create mode 100644 configs/a95x-z2-rk3318_defconfig
diff --git a/arch/arm/dts/rk3318-a95x-z2-u-boot.dtsi b/arch/arm/dts/rk3318-a95x-z2-u-boot.dtsi new file mode 100644 index 000000000000..e21fd6e07df7 --- /dev/null +++ b/arch/arm/dts/rk3318-a95x-z2-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3328-u-boot.dtsi" +#include "rk3328-sdram-ddr3-666.dtsi" + +&usb20_otg { + dr_mode = "otg"; +}; + diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 5f81be55b8e0..fe642a56a690 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -1,3 +1,9 @@ +A95X-Z2-RK3318 +M: Johan Jonker jbx6244@gmail.com +S: Maintained +F: configs/a95x-z2-rk3318_defconfig +F: arch/arm/dts/rk3318-a95x-z2-u-boot.dtsi + EVB-RK3328 M: Kever Yang kever.yang@rock-chips.com S: Maintained diff --git a/configs/a95x-z2-rk3318_defconfig b/configs/a95x-z2-rk3318_defconfig new file mode 100644 index 000000000000..9cb6a67ad5ae --- /dev/null +++ b/configs/a95x-z2-rk3318_defconfig @@ -0,0 +1,94 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3318-a95x-z2" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3318-a95x-z2.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NET is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +# CONFIG_NETDEVICES is not set +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 9bab86d23479..ec325c4fe558 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -57,6 +57,8 @@ List of mainline supported Rockchip boards: - Radxa ROCK S0 (rock-s0-rk3308) - Rockchip Evb-RK3308 (evb-rk3308) - Roc-cc-RK3308 (roc-cc-rk3308) +* rk3318 + - A95X Z2 (a95x-z2-rk3318) * rk3326 - ODROID-GO Advance (odroid-go2) * rk3328 @@ -190,7 +192,7 @@ TPL
For some SoCs U-Boot sources lack of support to inizialize DRAM. In these cases, to get a fully functional image following :ref:`PackageWithTPLandSPL`, use DDR binary provided by Rockchip rkbin repository as ROCKCHIP_TPL when building U-Boot. -Otherwise, follow :ref:`PackageWithRockchipMiniloader`. +Otherwise, follow :ref:`PackageWithRockchipMiniloader`.
U-Boot ^^^^^^ -- 2.39.5