Admittedly this is the long way round to solve some nasty SPL code size problem, but it looked beneficial to others as well, so here we go:
arch/arm/include/asm/io.h looks like it's been around since the dawn of time, and was more or less blindly copied from Linux. We don't use and don't need most of the definitions, and mainline Linux got rid of them anyway, so patch 1/3 cleans up this header file to just contain what we need in U-Boot.
Patch 2/3 introduces readl/writel_relaxed accessors, which are cheaper, but more importantly save one (barrier) instruction per accessor. This helps to bring down code size, since especially DRAM controller inits in SPLs tend to do a lot of MMIO.
Consequently patch 3/3 introduces them in the Allwinner H6 DRAM driver, which reduces the SPL size by a whopping 2KB, due to a twist: The AArch64 exception table needs to be 2KB aligned, but we don't do anything special about it the linker script. So depending on where the code before the vectors ends, we have potentially large padding: At the moment this last address is 0x1824 for the H6, so the vectors can only start at 0x2000. By reducing the code size before the vectors by just (at least) 9 instructions, the vectors start at 0x1800 and we save most of the padding.
I understand that the proper solution is to fill the gap before the vectors with code instead of NOPs, but I couldn't find any obvious way doing this in the linker script. If anyone has any idea here, I am all ears.
Cheers, Andre.
Andre Przywara (3): arm: clean up asm/io.h arm: introduce _relaxed MMIO accessors sunxi: H6: use writel_relaxed for DRAM timing register accesses
arch/arm/include/asm/io.h | 164 +++-------------------------------- arch/arm/mach-sunxi/dram_sun50i_h6.c | 79 +++++++++-------- 2 files changed, 54 insertions(+), 189 deletions(-)