On Sunday 22 October 2006 04:38, Leonid wrote:
[Leonid] Actually I could make spd_sdram work for my board (our HW guy hooked up DIMM EEPROM connections for me). I stepped through code using debugger and found out that EEPROM (address 0x51 on our board) has been successfully read, all parameters were sane and SDRAM registers have been updated accordantly.
OK. So far so good.
However sdram0_mcsts register's most significant bit never becomes 1, meaning SDRAM controller cannot complete memory initialization and code stays in endless loop:
/* * wait for SDRAM_CFG0_DC_EN to complete */ while (1) { mfsdram(mem_mcsts, mcsts); if ((mcsts & SDRAM_MCSTS_MRSC) != 0) { break; } }
That looks like HW problem for me.
Yes. I never have seen a board where this did not happen. Did you try to skip this test to see, if the DDR interface perhaps works without this bit set? (Just a test of course, no solution).
I have to admit, that I don't know what problems would result in this bit not being set, apart from DC_EN not set in the SDRAM0_CFG0 register.
Of course, I'll look through actual registers' values more carefully - may be spd_sdram() just parsed EEPROM parameters wrongly but I doubt that.
Just in case - did you happen to have BDI config file for that board - brief search in the ftp://ftp.denx.de/pub/BDI2000/ directory didn't provide results.
Yes. Please find it attached.
Best regards, Stefan