Hi,
Please ignore this patch 1/3, since "imx: mx6: Fixed AIPS3 base address issue" from Ye.Li already fix this. Patch 2/3 and patch 3/3 are fine. Please review.
On 1/15/2015 2:22 PM, Peng Fan wrote:
Signed-off-by: Peng Fan Peng.Fan@freescale.com
arch/arm/include/asm/arch-mx6/imx-regs.h | 50 ++++++++++++++++---------------- 1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5314298..44e31c9 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -277,31 +277,31 @@ #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
#ifdef CONFIG_MX6SX -#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) -#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) -#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) -#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) -#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) -#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) -#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) -#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) -#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) -#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) -#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) -#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) -#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) -#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) -#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) -#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) -#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) -#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) -#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) -#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) -#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) -#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) -#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) -#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) -#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) +#define GIS_BASE_ADDR (AIPS3_BASE_ADDR + 0x04000) +#define DCIC1_BASE_ADDR (AIPS3_BASE_ADDR + 0x0C000) +#define DCIC2_BASE_ADDR (AIPS3_BASE_ADDR + 0x10000) +#define CSI1_BASE_ADDR (AIPS3_BASE_ADDR + 0x14000) +#define PXP_BASE_ADDR (AIPS3_BASE_ADDR + 0x18000) +#define CSI2_BASE_ADDR (AIPS3_BASE_ADDR + 0x1C000) +#define LCDIF1_BASE_ADDR (AIPS3_BASE_ADDR + 0x20000) +#define LCDIF2_BASE_ADDR (AIPS3_BASE_ADDR + 0x24000) +#define VADC_BASE_ADDR (AIPS3_BASE_ADDR + 0x28000) +#define VDEC_BASE_ADDR (AIPS3_BASE_ADDR + 0x2C000) +#define SPBA_BASE_ADDR (AIPS3_BASE_ADDR + 0x3C000) +#define AIPS3_CONFIG_BASE_ADDR (AIPS3_BASE_ADDR + 0x7C000) +#define ADC1_BASE_ADDR (AIPS3_BASE_ADDR + 0x80000) +#define ADC2_BASE_ADDR (AIPS3_BASE_ADDR + 0x84000) +#define WDOG3_BASE_ADDR (AIPS3_BASE_ADDR + 0x88000) +#define ECSPI5_BASE_ADDR (AIPS3_BASE_ADDR + 0x8C000) +#define HS_BASE_ADDR (AIPS3_BASE_ADDR + 0x90000) +#define MU_MCU_BASE_ADDR (AIPS3_BASE_ADDR + 0x94000) +#define CANFD_BASE_ADDR (AIPS3_BASE_ADDR + 0x98000) +#define MU_DSP_BASE_ADDR (AIPS3_BASE_ADDR + 0x9C000) +#define UART6_BASE_ADDR (AIPS3_BASE_ADDR + 0xA0000) +#define PWM5_BASE_ADDR (AIPS3_BASE_ADDR + 0xA4000) +#define PWM6_BASE_ADDR (AIPS3_BASE_ADDR + 0xA8000) +#define PWM7_BASE_ADDR (AIPS3_BASE_ADDR + 0xAC000) +#define PWM8_BASE_ADDR (AIPS3_BASE_ADDR + 0xB0000) #endif
#define CHIP_REV_1_0 0x10
Thanks, Peng.