Ensure that cache operations complete before returning from mips_cache_reset by placing a completion barrier (sync instruction) before the return. Without this there is no guarantee that the cache ops will complete before any subsequent memory accesses, since they are indexed cache ops & thus not implicitly ordered with memory accesses.
Signed-off-by: Paul Burton paul.burton@imgtec.com
---
Changes in v3: - New patch
Changes in v2: None
arch/mips/lib/cache_init.S | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 53e903a..698a5af 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -420,6 +420,8 @@ l2_unbypass: #endif
return: + /* Ensure all cache operations complete before returning */ + sync jr ra END(mips_cache_reset)