I'd built 1.2.0 for the MPC8548 CDS, and put that on an earlier board which worked fine. Then I went to install it on a newer board (e500v2) and the same image was giving me an illegal instruction fault. Once I saw the latest git trees gave me the same error, I went back in time and started poking around older versions and eventually tracked it down to the timer IRQ support. Here is the patch I'm running now -- this may not be the desired long term fix, but at least it will save people the detective work part (which was kind of nasty, as the PHY code shows up as the culprit, just out of coincidence...)
Thanks, Paul.
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The interrupt support is broken on newer e500v2 boards. Trying to enable it will result in an illegal instruction trap once the 1st TCR_PIE event happens, which will roughly be around the PHY detection for the TSEC (depending on your CPU speed). Since the interrupt generation is only used for the periodic timer interrupts, which are in turn only used if you are using the u-boot watchdog, a fix is to just disable it as per pre-1.1.4 u-boot versions.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com
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--- orig/u-boot-1.2.0/cpu/mpc85xx/interrupts.c 2007-01-06 18:13:11.000000000 -0500 +++ u-boot-1.2.0/cpu/mpc85xx/interrupts.c 2007-05-23 21:15:20.000000000 -0400 @@ -80,6 +80,7 @@
int interrupt_init (void) { +#ifdef CONFIG_MPC85xx_TIMER_IRQ volatile immap_t *immr = (immap_t *)CFG_IMMR;
immr->im_pic.gcr = MPC85xx_PICGCR_RST; @@ -89,6 +90,7 @@ mtspr(SPRN_TCR, TCR_PIE); set_dec (decrementer_count); set_msr (get_msr () | MSR_EE); +#endif /* CONFIG_MPC85xx_TIMER_IRQ */ return (0); }