add DM/DTS suppor for the UEC ethernet on QUICC Engine Block.
Signed-off-by: Heiko Schocher hs@denx.de --- Travis build:
https://travis-ci.org/hsdenx/u-boot-test/builds/651400509
- I let the old none DM based implementation in code so boards should work with old implementation. This Code should be removed if all boards are converted to DM/DTS.
- add the DM based qe uec driver under drivers/net/qe
- Therefore copied the files uccf.c uccf.h uec.h from drivers/qe. So there are a lot of Codingstyle problems currently. I fix them in next version if this RFC patch is OK or it needs some changes.
- The dm based driver code is now under drivers/net/qe/dm_qe_uec.c Used a lot of functions from drivers/qe/uec.c
- seperated the PHY specific code into seperate file drivers/net/qe/dm_qe_uec_phy.c
drivers/net/Kconfig | 2 + drivers/net/Makefile | 1 + drivers/net/qe/Kconfig | 9 + drivers/net/qe/Makefile | 5 + drivers/net/qe/dm_qe_uec.c | 1161 ++++++++++++++++++++++++++++++++ drivers/net/qe/dm_qe_uec.h | 22 + drivers/net/qe/dm_qe_uec_phy.c | 161 +++++ drivers/net/qe/uccf.c | 388 +++++++++++ drivers/net/qe/uccf.h | 117 ++++ drivers/net/qe/uec.h | 742 ++++++++++++++++++++ drivers/qe/uccf.c | 2 + drivers/qe/uec.c | 2 + drivers/qe/uec_phy.c | 3 + 13 files changed, 2615 insertions(+) create mode 100644 drivers/net/qe/Kconfig create mode 100644 drivers/net/qe/Makefile create mode 100644 drivers/net/qe/dm_qe_uec.c create mode 100644 drivers/net/qe/dm_qe_uec.h create mode 100644 drivers/net/qe/dm_qe_uec_phy.c create mode 100644 drivers/net/qe/uccf.c create mode 100644 drivers/net/qe/uccf.h create mode 100644 drivers/net/qe/uec.h
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 4d1013c984..6bb84e3d2b 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -371,6 +371,8 @@ config MII help Enable support of the Media-Independent Interface (MII)
+source "drivers/net/qe/Kconfig" + config RTL8139 bool "Realtek 8139 series Ethernet controller driver" help diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 6e0a68834d..cc892d718f 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_VSC9953) += vsc9953.o obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ +obj-y += qe/ obj-$(CONFIG_SNI_AVE) += sni_ave.o obj-y += ti/ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o diff --git a/drivers/net/qe/Kconfig b/drivers/net/qe/Kconfig new file mode 100644 index 0000000000..dec88dea2a --- /dev/null +++ b/drivers/net/qe/Kconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Heiko Schocher hs@denx.de + +config QE_UEC + bool "NXP QE UEC Ethernet controller" + depends on DM_ETH + help + This driver supports the NXP QE UEC ethernet controller diff --git a/drivers/net/qe/Makefile b/drivers/net/qe/Makefile new file mode 100644 index 0000000000..7d84757c17 --- /dev/null +++ b/drivers/net/qe/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Heiko Schocher hs@denx.de + +obj-$(CONFIG_QE_UEC) += dm_qe_uec.o dm_qe_uec_phy.o uccf.o diff --git a/drivers/net/qe/dm_qe_uec.c b/drivers/net/qe/dm_qe_uec.c new file mode 100644 index 0000000000..119e47dc20 --- /dev/null +++ b/drivers/net/qe/dm_qe_uec.c @@ -0,0 +1,1161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * QE UEC ethernet controller driver + * + * based on drivers/qe/uec.c from NXP + * + * Copyright (C) 2020 Heiko Schocher hs@denx.de + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <memalign.h> +#include <miiphy.h> +#include <asm/io.h> + +#include "dm_qe_uec.h" + +#define QE_UEC_DRIVER_NAME "ucc_geth" + +/* Default UTBIPAR SMI address */ +#ifndef CONFIG_UTBIPAR_INIT_TBIPA +#define CONFIG_UTBIPAR_INIT_TBIPA 0x1F +#endif + +static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode) +{ + uec_t *uec_regs; + u32 maccfg1; + + uec_regs = uec->uec_regs; + maccfg1 = in_be32(&uec_regs->maccfg1); + + if (mode & COMM_DIR_TX) { + maccfg1 |= MACCFG1_ENABLE_TX; + out_be32(&uec_regs->maccfg1, maccfg1); + uec->mac_tx_enabled = 1; + } + + if (mode & COMM_DIR_RX) { + maccfg1 |= MACCFG1_ENABLE_RX; + out_be32(&uec_regs->maccfg1, maccfg1); + uec->mac_rx_enabled = 1; + } + + return 0; +} + +static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode) +{ + uec_t *uec_regs; + u32 maccfg1; + + uec_regs = uec->uec_regs; + maccfg1 = in_be32(&uec_regs->maccfg1); + + if (mode & COMM_DIR_TX) { + maccfg1 &= ~MACCFG1_ENABLE_TX; + out_be32(&uec_regs->maccfg1, maccfg1); + uec->mac_tx_enabled = 0; + } + + if (mode & COMM_DIR_RX) { + maccfg1 &= ~MACCFG1_ENABLE_RX; + out_be32(&uec_regs->maccfg1, maccfg1); + uec->mac_rx_enabled = 0; + } + + return 0; +} + +static int uec_restart_tx(uec_private_t *uec) +{ + uec_info_t *ui = uec->uec_info; + u32 cecr_subblock; + + cecr_subblock = ucc_fast_get_qe_cr_subblock(ui->uf_info.ucc_num); + qe_issue_cmd(QE_RESTART_TX, cecr_subblock, + (u8)QE_CR_PROTOCOL_ETHERNET, 0); + + uec->grace_stopped_tx = 0; + + return 0; +} + +static int uec_restart_rx(uec_private_t *uec) +{ + uec_info_t *ui = uec->uec_info; + u32 cecr_subblock; + + cecr_subblock = ucc_fast_get_qe_cr_subblock(ui->uf_info.ucc_num); + qe_issue_cmd(QE_RESTART_RX, cecr_subblock, + (u8)QE_CR_PROTOCOL_ETHERNET, 0); + + uec->grace_stopped_rx = 0; + + return 0; +} + +static int uec_open(uec_private_t *uec, comm_dir_e mode) +{ + ucc_fast_private_t *uccf; + + uccf = uec->uccf; + + /* check if the UCC number is in range. */ + if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { + printf("%s: ucc_num out of range.\n", __func__); + return -EINVAL; + } + + /* Enable MAC */ + uec_mac_enable(uec, mode); + + /* Enable UCC fast */ + ucc_fast_enable(uccf, mode); + + /* RISC microcode start */ + if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) + uec_restart_tx(uec); + + if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) + uec_restart_rx(uec); + + return 0; +} + +static int uec_set_mac_if_mode(uec_private_t *uec) +{ + uec_info_t *uec_info = uec->uec_info; + phy_interface_t enet_if_mode; + uec_t *uec_regs; + u32 upsmr; + u32 maccfg2; + + uec_regs = uec->uec_regs; + enet_if_mode = uec_info->enet_interface_type; + + maccfg2 = in_be32(&uec_regs->maccfg2); + maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK; + + upsmr = in_be32(&uec->uccf->uf_regs->upsmr); + upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM); + + switch (uec_info->speed) { + case SPEED_10: + maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; + switch (enet_if_mode) { + case PHY_INTERFACE_MODE_MII: + break; + case PHY_INTERFACE_MODE_RGMII: + upsmr |= (UPSMR_RPM | UPSMR_R10M); + break; + case PHY_INTERFACE_MODE_RMII: + upsmr |= (UPSMR_R10M | UPSMR_RMM); + break; + default: + return -EINVAL; + break; + } + break; + case SPEED_100: + maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; + switch (enet_if_mode) { + case PHY_INTERFACE_MODE_MII: + break; + case PHY_INTERFACE_MODE_RGMII: + upsmr |= UPSMR_RPM; + break; + case PHY_INTERFACE_MODE_RMII: + upsmr |= UPSMR_RMM; + break; + default: + return -EINVAL; + break; + } + break; + case SPEED_1000: + maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; + switch (enet_if_mode) { + case PHY_INTERFACE_MODE_GMII: + break; + case PHY_INTERFACE_MODE_TBI: + upsmr |= UPSMR_TBIM; + break; + case PHY_INTERFACE_MODE_RTBI: + upsmr |= (UPSMR_RPM | UPSMR_TBIM); + break; + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII: + upsmr |= UPSMR_RPM; + break; + case PHY_INTERFACE_MODE_SGMII: + upsmr |= UPSMR_SGMM; + break; + default: + return -EINVAL; + break; + } + break; + default: + return -EINVAL; + break; + } + + out_be32(&uec_regs->maccfg2, maccfg2); + out_be32(&uec->uccf->uf_regs->upsmr, upsmr); + + return 0; +} + +static int qe_uec_start(struct udevice *dev) +{ + struct qe_uec_priv *priv = dev_get_priv(dev); + uec_private_t *uec = priv->uec; + struct phy_device *phydev = priv->phydev; + uec_info_t *uec_info = uec->uec_info; + int err; + + if (!phydev) + return -ENODEV; + + /* Setup MAC interface mode */ + genphy_update_link(phydev); + genphy_parse_link(phydev); + uec_info->speed = phydev->speed; + uec_set_mac_if_mode(uec); + + err = uec_open(uec, COMM_DIR_RX_AND_TX); + if (err) { + printf("%s: cannot enable UEC device\n", dev->name); + return -EINVAL; + } + + return (phydev->link ? 0 : -EINVAL); +} + +static int qe_uec_send(struct udevice *dev, void *packet, int length) +{ + struct qe_uec_priv *priv = dev_get_priv(dev); + uec_private_t *uec = priv->uec; + ucc_fast_private_t *uccf = uec->uccf; + volatile qe_bd_t *bd = uec->txBd; + u16 status; + int i; + int result = 0; + + /* Find an empty TxBD */ + for (i = 0; bd->status & TxBD_READY; i++) { + if (i > 0x100000) { + printf("%s: tx buffer not ready\n", dev->name); + return result; + } + } + + /* Init TxBD */ + BD_DATA_SET(bd, packet); + BD_LENGTH_SET(bd, length); + status = bd->status; + status &= BD_WRAP; + status |= (TxBD_READY | TxBD_LAST); + BD_STATUS_SET(bd, status); + + /* Tell UCC to transmit the buffer */ + ucc_fast_transmit_on_demand(uccf); + + /* Wait for buffer to be transmitted */ + for (i = 0; bd->status & TxBD_READY; i++) { + if (i > 0x100000) { + printf("%s: tx error\n", dev->name); + return result; + } + } + + /* Ok, the buffer be transimitted */ + BD_ADVANCE(bd, status, uec->p_tx_bd_ring); + uec->txBd = bd; + result = 1; + + return result; +} + +/* + * Receive frame: + * - wait for the next BD to get ready bit set + * - clean up the descriptor + * - move on and indicate to HW that the cleaned BD is available for Rx + */ +static int qe_uec_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct qe_uec_priv *priv = dev_get_priv(dev); + uec_private_t *uec = priv->uec; + volatile qe_bd_t *bd = uec->rxBd; + u16 status; + u16 len = 0; + u8 *data; + + *packetp = memalign(ARCH_DMA_MINALIGN, MAX_RXBUF_LEN); + if (*packetp == 0) { + printf("%s: error allocating packetp\n", __func__); + return -ENOMEM; + } + + bd = uec->rxBd; + status = bd->status; + + while (!(status & RxBD_EMPTY)) { + if (!(status & RxBD_ERROR)) { + data = BD_DATA(bd); + len = BD_LENGTH(bd); + memcpy(*packetp, (char *)data, len); + } else { + printf("%s: Rx error\n", dev->name); + } + status &= BD_CLEAN; + BD_LENGTH_SET(bd, 0); + BD_STATUS_SET(bd, status | RxBD_EMPTY); + BD_ADVANCE(bd, status, uec->p_rx_bd_ring); + status = bd->status; + } + uec->rxBd = bd; + + return len; +} + +static int uec_graceful_stop_tx(uec_private_t *uec) +{ + ucc_fast_t *uf_regs; + u32 cecr_subblock; + u32 ucce; + + uf_regs = uec->uccf->uf_regs; + + /* Clear the grace stop event */ + out_be32(&uf_regs->ucce, UCCE_GRA); + + /* Issue host command */ + cecr_subblock = + ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); + qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, + (u8)QE_CR_PROTOCOL_ETHERNET, 0); + + /* Wait for command to complete */ + do { + ucce = in_be32(&uf_regs->ucce); + } while (! (ucce & UCCE_GRA)); + + uec->grace_stopped_tx = 1; + + return 0; +} + +static int uec_graceful_stop_rx(uec_private_t *uec) +{ + u32 cecr_subblock; + u8 ack; + + if (!uec->p_rx_glbl_pram) { + printf("%s: No init rx global parameter\n", __func__); + return -EINVAL; + } + + /* Clear acknowledge bit */ + ack = uec->p_rx_glbl_pram->rxgstpack; + ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX; + uec->p_rx_glbl_pram->rxgstpack = ack; + + /* Keep issuing cmd and checking ack bit until it is asserted */ + do { + /* Issue host command */ + cecr_subblock = + ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); + qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock, + (u8)QE_CR_PROTOCOL_ETHERNET, 0); + ack = uec->p_rx_glbl_pram->rxgstpack; + } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX )); + + uec->grace_stopped_rx = 1; + + return 0; +} + + +static int uec_stop(uec_private_t *uec, comm_dir_e mode) +{ + /* check if the UCC number is in range. */ + if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { + printf("%s: ucc_num out of range.\n", __func__); + return -EINVAL; + } + /* Stop any transmissions */ + if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) + uec_graceful_stop_tx(uec); + + /* Stop any receptions */ + if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) + uec_graceful_stop_rx(uec); + + /* Disable the UCC fast */ + ucc_fast_disable(uec->uccf, mode); + + /* Disable the MAC */ + uec_mac_disable(uec, mode); + + return 0; +} + +static void qe_uec_stop(struct udevice *dev) +{ + struct qe_uec_priv *priv = dev_get_priv(dev); + uec_private_t *uec = priv->uec; + + uec_stop(uec, COMM_DIR_RX_AND_TX); + return; +} + +static int qe_uec_set_hwaddr(struct udevice *dev) +{ + struct qe_uec_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + struct uec_private *uec = priv->uec; + uec_t *uec_regs = uec->uec_regs; + uchar *mac = pdata->enetaddr; + u32 mac_addr1; + u32 mac_addr2; + + /* + * if a station address of 0x12345678ABCD, perform a write to + * MACSTNADDR1 of 0xCDAB7856, + * MACSTNADDR2 of 0x34120000 + */ + + mac_addr1 = (mac[5] << 24) | (mac[4] << 16) | \ + (mac[3] << 8) | (mac[2]); + out_be32(&uec_regs->macstnaddr1, mac_addr1); + + mac_addr2 = ((mac[1] << 24) | (mac[0] << 16)) & 0xffff0000; + out_be32(&uec_regs->macstnaddr2, mac_addr2); + + return 0; +} +static int qe_uec_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + if (packet) + free(packet); + + return 0; +} + +static const struct eth_ops qe_uec_eth_ops = { + .start = qe_uec_start, + .send = qe_uec_send, + .recv = qe_uec_recv, + .free_pkt = qe_uec_free_pkt, + .stop = qe_uec_stop, + .write_hwaddr = qe_uec_set_hwaddr, +}; + +static int uec_convert_threads_num(uec_num_of_threads_e threads_num, + int *threads_num_ret) +{ + int num_threads_numerica; + + switch (threads_num) { + case UEC_NUM_OF_THREADS_1: + num_threads_numerica = 1; + break; + case UEC_NUM_OF_THREADS_2: + num_threads_numerica = 2; + break; + case UEC_NUM_OF_THREADS_4: + num_threads_numerica = 4; + break; + case UEC_NUM_OF_THREADS_6: + num_threads_numerica = 6; + break; + case UEC_NUM_OF_THREADS_8: + num_threads_numerica = 8; + break; + default: + printf("%s: Bad number of threads value.", + __FUNCTION__); + return -EINVAL; + } + + *threads_num_ret = num_threads_numerica; + + return 0; +} + +static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx) +{ + uec_info_t *uec_info; + u32 end_bd; + u8 bmrx = 0; + int i; + + uec_info = uec->uec_info; + + /* Alloc global Tx parameter RAM page */ + uec->tx_glbl_pram_offset = qe_muram_alloc( + sizeof(uec_tx_global_pram_t), + UEC_TX_GLOBAL_PRAM_ALIGNMENT); + uec->p_tx_glbl_pram = (uec_tx_global_pram_t *) + qe_muram_addr(uec->tx_glbl_pram_offset); + + /* Zero the global Tx prameter RAM */ + memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t)); + + /* Init global Tx parameter RAM */ + + /* TEMODER, RMON statistics disable, one Tx queue */ + out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE); + + /* SQPTR */ + uec->send_q_mem_reg_offset = qe_muram_alloc( + sizeof(uec_send_queue_qd_t), + UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT); + uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *) + qe_muram_addr(uec->send_q_mem_reg_offset); + out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset); + + /* Setup the table with TxBDs ring */ + end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1) + * SIZEOFBD; + out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base, + (u32)(uec->p_tx_bd_ring)); + out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address, + end_bd); + + /* Scheduler Base Pointer, we have only one Tx queue, no need it */ + out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0); + + /* TxRMON Base Pointer, TxRMON disable, we don't need it */ + out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0); + + /* TSTATE, global snooping, big endian, the CSB bus selected */ + bmrx = BMR_INIT_VALUE; + out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT)); + + /* IPH_Offset */ + for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) + out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0); + + /* VTAG table */ + for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) + out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0); + + /* TQPTR */ + uec->thread_dat_tx_offset = qe_muram_alloc( + num_threads_tx * sizeof(uec_thread_data_tx_t) + + 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT); + + uec->p_thread_data_tx = (uec_thread_data_tx_t *) + qe_muram_addr(uec->thread_dat_tx_offset); + out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset); +} + +static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx) +{ + u8 bmrx = 0; + int i; + uec_82xx_address_filtering_pram_t *p_af_pram; + + /* Allocate global Rx parameter RAM page */ + uec->rx_glbl_pram_offset = qe_muram_alloc( + sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT); + uec->p_rx_glbl_pram = (uec_rx_global_pram_t *) + qe_muram_addr(uec->rx_glbl_pram_offset); + + /* Zero Global Rx parameter RAM */ + memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t)); + + /* Init global Rx parameter RAM */ + /* REMODER, Extended feature mode disable, VLAN disable, + LossLess flow control disable, Receive firmware statisic disable, + Extended address parsing mode disable, One Rx queues, + Dynamic maximum/minimum frame length disable, IP checksum check + disable, IP address alignment disable + */ + out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE); + + /* RQPTR */ + uec->thread_dat_rx_offset = qe_muram_alloc( + num_threads_rx * sizeof(uec_thread_data_rx_t), + UEC_THREAD_DATA_ALIGNMENT); + uec->p_thread_data_rx = (uec_thread_data_rx_t *) + qe_muram_addr(uec->thread_dat_rx_offset); + out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset); + + /* Type_or_Len */ + out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072); + + /* RxRMON base pointer, we don't need it */ + out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0); + + /* IntCoalescingPTR, we don't need it, no interrupt */ + out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0); + + /* RSTATE, global snooping, big endian, the CSB bus selected */ + bmrx = BMR_INIT_VALUE; + out_8(&uec->p_rx_glbl_pram->rstate, bmrx); + + /* MRBLR */ + out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN); + + /* RBDQPTR */ + uec->rx_bd_qs_tbl_offset = qe_muram_alloc( + sizeof(uec_rx_bd_queues_entry_t) + \ + sizeof(uec_rx_prefetched_bds_t), + UEC_RX_BD_QUEUES_ALIGNMENT); + uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *) + qe_muram_addr(uec->rx_bd_qs_tbl_offset); + + /* Zero it */ + memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \ + sizeof(uec_rx_prefetched_bds_t)); + out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset); + out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr, + (u32)uec->p_rx_bd_ring); + + /* MFLR */ + out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN); + /* MINFLR */ + out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN); + /* MAXD1 */ + out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN); + /* MAXD2 */ + out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN); + /* ECAM_PTR */ + out_be32(&uec->p_rx_glbl_pram->ecamptr, 0); + /* L2QT */ + out_be32(&uec->p_rx_glbl_pram->l2qt, 0); + /* L3QT */ + for (i = 0; i < 8; i++) + out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0); + + /* VLAN_TYPE */ + out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100); + /* TCI */ + out_be16(&uec->p_rx_glbl_pram->vlantci, 0); + + /* Clear PQ2 style address filtering hash table */ + p_af_pram = (uec_82xx_address_filtering_pram_t *) \ + uec->p_rx_glbl_pram->addressfiltering; + + p_af_pram->iaddr_h = 0; + p_af_pram->iaddr_l = 0; + p_af_pram->gaddr_h = 0; + p_af_pram->gaddr_l = 0; +} + +static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec, + int thread_tx, int thread_rx) +{ + uec_init_cmd_pram_t *p_init_enet_param; + u32 init_enet_param_offset; + uec_info_t *uec_info; + int i; + int snum; + u32 init_enet_offset; + u32 entry_val; + u32 command; + u32 cecr_subblock; + + uec_info = uec->uec_info; + + /* Allocate init enet command parameter */ + uec->init_enet_param_offset = qe_muram_alloc( + sizeof(uec_init_cmd_pram_t), 4); + init_enet_param_offset = uec->init_enet_param_offset; + uec->p_init_enet_param = (uec_init_cmd_pram_t *) + qe_muram_addr(uec->init_enet_param_offset); + + /* Zero init enet command struct */ + memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t)); + + /* Init the command struct */ + p_init_enet_param = uec->p_init_enet_param; + p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0; + p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1; + p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2; + p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3; + p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4; + p_init_enet_param->largestexternallookupkeysize = 0; + + p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx) + << ENET_INIT_PARAM_RGF_SHIFT; + p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx) + << ENET_INIT_PARAM_TGF_SHIFT; + + /* Init Rx global parameter pointer */ + p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset | + (u32)uec_info->risc_rx; + + /* Init Rx threads */ + for (i = 0; i < (thread_rx + 1); i++) { + if ((snum = qe_get_snum()) < 0) { + printf("%s can not get snum\n", __func__); + return -ENOMEM; + } + + if (i==0) { + init_enet_offset = 0; + } else { + init_enet_offset = qe_muram_alloc( + sizeof(uec_thread_rx_pram_t), + UEC_THREAD_RX_PRAM_ALIGNMENT); + } + + entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) | + init_enet_offset | (u32)uec_info->risc_rx; + p_init_enet_param->rxthread[i] = entry_val; + } + + /* Init Tx global parameter pointer */ + p_init_enet_param->txglobal = uec->tx_glbl_pram_offset | + (u32)uec_info->risc_tx; + + /* Init Tx threads */ + for (i = 0; i < thread_tx; i++) { + if ((snum = qe_get_snum()) < 0) { + printf("%s can not get snum\n", __func__); + return -ENOMEM; + } + + init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t), + UEC_THREAD_TX_PRAM_ALIGNMENT); + + entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) | + init_enet_offset | (u32)uec_info->risc_tx; + p_init_enet_param->txthread[i] = entry_val; + } + + __asm__ __volatile__("sync"); + + /* Issue QE command */ + command = QE_INIT_TX_RX; + cecr_subblock = ucc_fast_get_qe_cr_subblock( + uec_info->uf_info.ucc_num); + qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET, + init_enet_param_offset); + + return 0; +} + +static int uec_startup(struct udevice *dev) +{ + struct qe_uec_priv *priv = dev_get_priv(dev); + uec_private_t *uec = priv->uec; + uec_info_t *uec_info; + ucc_fast_info_t *uf_info; + ucc_fast_private_t *uccf; + ucc_fast_t *uf_regs; + uec_t *uec_regs; + int num_threads_tx; + int num_threads_rx; + u32 utbipar; + u32 length; + u32 align; + qe_bd_t *bd; + u8 *buf; + int i; + + uec_info = uec->uec_info; + uf_info = &(uec_info->uf_info); + + /* Check if Rx BD ring len is illegal */ + if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \ + (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) { + printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n", + __func__); + return -EINVAL; + } + + /* Check if Tx BD ring len is illegal */ + if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) { + printf("%s: Tx BD ring length must not be smaller than 2.\n", + __func__); + return -EINVAL; + } + + /* Check if MRBLR is illegal */ + if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) { + printf("%s: max rx buffer length must be mutliple of 128.\n", + __func__); + return -EINVAL; + } + + /* Both Rx and Tx are stopped */ + uec->grace_stopped_rx = 1; + uec->grace_stopped_tx = 1; + + /* Init UCC fast */ + if (ucc_fast_init(uf_info, &uccf)) { + printf("%s: failed to init ucc fast\n", __func__); + return -ENOMEM; + } + + /* Save uccf */ + uec->uccf = uccf; + + /* Convert the Tx threads number */ + if (uec_convert_threads_num(uec_info->num_threads_tx, + &num_threads_tx)) + return -EINVAL; + + /* Convert the Rx threads number */ + if (uec_convert_threads_num(uec_info->num_threads_rx, + &num_threads_rx)) + return -EINVAL; + + uf_regs = uccf->uf_regs; + + /* UEC register is following UCC fast registers */ + uec_regs = (uec_t *)(&uf_regs->ucc_eth); + + /* Save the UEC register pointer to UEC private struct */ + uec->uec_regs = uec_regs; + + /* Init UPSMR, enable hardware statistics (UCC) */ + out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE); + + /* Init MACCFG1, flow control disable, disable Tx and Rx */ + out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE); + + /* Init MACCFG2, length check, MAC PAD and CRC enable */ + out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE); + + /* Setup UTBIPAR */ + utbipar = in_be32(&uec_regs->utbipar); + utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK; + + /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC. + * This frees up the remaining SMI addresses for use. + */ + utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT; + out_be32(&uec_regs->utbipar, utbipar); + + /* Allocate Tx BDs */ + length = ((uec_info->tx_bd_ring_len * SIZEOFBD) / + UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) * + UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; + if ((uec_info->tx_bd_ring_len * SIZEOFBD) % + UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) + length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; + + align = UEC_TX_BD_RING_ALIGNMENT; + uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align)); + if (uec->tx_bd_ring_offset != 0) + uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align) + & ~(align - 1)); + + /* Zero all of Tx BDs */ + memset((void *)(uec->tx_bd_ring_offset), 0, length + align); + + /* Allocate Rx BDs */ + length = uec_info->rx_bd_ring_len * SIZEOFBD; + align = UEC_RX_BD_RING_ALIGNMENT; + uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align))); + if (uec->rx_bd_ring_offset != 0) + uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align) + & ~(align - 1)); + + /* Zero all of Rx BDs */ + memset((void *)(uec->rx_bd_ring_offset), 0, length + align); + + /* Allocate Rx buffer */ + length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN; + align = UEC_RX_DATA_BUF_ALIGNMENT; + uec->rx_buf_offset = (u32)malloc(length + align); + if (uec->rx_buf_offset != 0) + uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align) + & ~(align - 1)); + + /* Zero all of the Rx buffer */ + memset((void *)(uec->rx_buf_offset), 0, length + align); + + /* Init TxBD ring */ + bd = (qe_bd_t *)uec->p_tx_bd_ring; + uec->txBd = bd; + + for (i = 0; i < uec_info->tx_bd_ring_len; i++) { + BD_DATA_CLEAR(bd); + BD_STATUS_SET(bd, 0); + BD_LENGTH_SET(bd, 0); + bd ++; + } + BD_STATUS_SET((--bd), TxBD_WRAP); + + /* Init RxBD ring */ + bd = (qe_bd_t *)uec->p_rx_bd_ring; + uec->rxBd = bd; + buf = uec->p_rx_buf; + for (i = 0; i < uec_info->rx_bd_ring_len; i++) { + BD_DATA_SET(bd, buf); + BD_LENGTH_SET(bd, 0); + BD_STATUS_SET(bd, RxBD_EMPTY); + buf += MAX_RXBUF_LEN; + bd ++; + } + BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY); + + /* Init global Tx parameter RAM */ + uec_init_tx_parameter(uec, num_threads_tx); + + /* Init global Rx parameter RAM */ + uec_init_rx_parameter(uec, num_threads_rx); + + /* Init ethernet Tx and Rx parameter command */ + if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx, + num_threads_rx)) { + printf("%s issue init enet cmd failed\n", __func__); + return -ENOMEM; + } + return 0; +} + +/* Convert a string to a QE clock source enum + * + * This function takes a string, typically from a property in the device + * tree, and returns the corresponding "enum qe_clock" value. +*/ +enum qe_clock qe_clock_source(const char *source) +{ + unsigned int i; + + if (strcasecmp(source, "none") == 0) + return QE_CLK_NONE; + + if (strncasecmp(source, "brg", 3) == 0) { + i = simple_strtoul(source + 3, NULL, 10); + if ((i >= 1) && (i <= 16)) + return (QE_BRG1 - 1) + i; + else + return QE_CLK_DUMMY; + } + + if (strncasecmp(source, "clk", 3) == 0) { + i = simple_strtoul(source + 3, NULL, 10); + if ((i >= 1) && (i <= 24)) + return (QE_CLK1 - 1) + i; + else + return QE_CLK_DUMMY; + } + + return QE_CLK_DUMMY; +} + +static void qe_uec_set_eth_type(struct udevice *dev) +{ + struct qe_uec_priv *priv = dev_get_priv(dev); + uec_private_t *uec = priv->uec; + uec_info_t *uec_info = uec->uec_info; + ucc_fast_info_t *uf_info = &uec_info->uf_info; + + switch (uec_info->enet_interface_type) { + case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_TBI: + case PHY_INTERFACE_MODE_RTBI: + case PHY_INTERFACE_MODE_SGMII: + uf_info->eth_type = GIGA_ETH; + break; + default: + uf_info->eth_type = FAST_ETH; + break; + } + return; +} + +static int qe_uec_set_uec_info(struct udevice *dev) +{ + struct qe_uec_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + uec_private_t *uec = priv->uec; + uec_info_t *uec_info; + ucc_fast_info_t *uf_info; + const char *s; + int ret; + u32 val; + + uec_info = (uec_info_t *)malloc(sizeof(uec_info_t)); + if (!uec_info) + return -ENOMEM; + + uf_info = &uec_info->uf_info; + + ret = dev_read_u32(dev, "cell-index", &val); + if (ret) { + ret = dev_read_u32(dev, "device-id", &val); + if (ret) { + pr_err("no cell-index nor device-id found!"); + goto out; + } + } + + uf_info->ucc_num = val - 1; + if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > 7)) { + ret = -ENODEV; + goto out; + } + + ret = dev_read_string_index(dev, "rx-clock-name", 0, &s); + if (!ret) { + uf_info->rx_clock = qe_clock_source(s); + if ((uf_info->rx_clock < QE_CLK_NONE) || + (uf_info->rx_clock > QE_CLK24)) { + pr_err("invalid rx-clock-name property\n"); + ret = -EINVAL; + goto out; + } + } else { + ret = dev_read_u32(dev, "rx-clock", &val); + if (ret) { + /* If both rx-clock-name and rx-clock are missing, + we want to tell people to use rx-clock-name. */ + pr_err("missing rx-clock-name property\n"); + goto out; + } + if ((val < QE_CLK_NONE) || (val > QE_CLK24)) { + pr_err("invalid rx-clock property\n"); + ret = -EINVAL; + goto out; + } + uf_info->rx_clock = val; + } + + ret = dev_read_string_index(dev, "tx-clock-name", 0, &s); + if (!ret) { + uf_info->tx_clock = qe_clock_source(s); + if ((uf_info->tx_clock < QE_CLK_NONE) || + (uf_info->tx_clock > QE_CLK24)) { + pr_err("invalid tx-clock-name property\n"); + ret = -EINVAL; + goto out; + } + } else { + ret = dev_read_u32(dev, "tx-clock", &val); + if (ret) { + pr_err("missing tx-clock-name property\n"); + goto out; + } + if ((val < QE_CLK_NONE) || (val > QE_CLK24)) { + pr_err("invalid tx-clock property\n"); + ret = -EINVAL; + goto out; + } + uf_info->tx_clock = val; + } + + uec_info->num_threads_tx = UEC_NUM_OF_THREADS_1; + uec_info->num_threads_rx = UEC_NUM_OF_THREADS_1; + uec_info->risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2; + uec_info->risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2; + uec_info->tx_bd_ring_len = 16; + uec_info->rx_bd_ring_len = 16; +#if (MAX_QE_RISC == 4) + uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS; + uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS; +#endif + + uec_info->enet_interface_type = pdata->phy_interface; + + uec->uec_info = uec_info; + qe_uec_set_eth_type(dev); + + return 0; +out: + free(uec_info); + return ret; +} + +static int qe_uec_probe(struct udevice *dev) +{ + struct qe_uec_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + uec_private_t *uec; + int ret; + + /* Allocate the UEC private struct */ + uec = (uec_private_t *)malloc(sizeof(uec_private_t)); + if (!uec) + return -ENOMEM; + + memset(uec, 0, sizeof(uec_private_t)); + priv->uec = uec; + uec->uec_regs = (uec_t *)pdata->iobase; + + /* setup uec info struct */ + ret = qe_uec_set_uec_info(dev); + if (ret) { + free(uec); + return ret; + } + + ret = uec_startup(dev); + if (ret) { + free(uec->uec_info); + free(uec); + return ret; + } + + priv->phydev = dm_eth_phy_connect(dev); + return 0; +} + +/* + * Remove the driver from an interface: + * - free up allocated memory + */ +static int qe_uec_remove(struct udevice *dev) +{ + struct qe_uec_priv *priv = dev_get_priv(dev); + + free(priv->uec); + return 0; +} + +static int qe_uec_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + const char *phy_mode; + + pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); + + pdata->phy_interface = -1; + phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), + "phy-connection-type", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + return 0; +} + + +static const struct udevice_id qe_uec_ids[] = { + { .compatible = QE_UEC_DRIVER_NAME }, + { } +}; + +U_BOOT_DRIVER(eth_qe_uec) = { + .name = QE_UEC_DRIVER_NAME, + .id = UCLASS_ETH, + .of_match = qe_uec_ids, + .ofdata_to_platdata = qe_uec_ofdata_to_platdata, + .probe = qe_uec_probe, + .remove = qe_uec_remove, + .ops = &qe_uec_eth_ops, + .priv_auto_alloc_size = sizeof(struct qe_uec_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/drivers/net/qe/dm_qe_uec.h b/drivers/net/qe/dm_qe_uec.h new file mode 100644 index 0000000000..12bb9b3d49 --- /dev/null +++ b/drivers/net/qe/dm_qe_uec.h @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * QE UEC ethernet controller driver + * + * based on drivers/qe/uec.c from NXP + * + * Copyright (C) 2020 Heiko Schocher hs@denx.de + */ + +#ifndef _DM_QE_UEC_H +#define _DM_QE_UEC_H + +#define qe_uec_dbg(dev, fmt, args...) debug("%s:" fmt, dev->name, ##args) + +#include "uec.h" + +/* QE UEC private structure */ +struct qe_uec_priv { + struct uec_private *uec; + struct phy_device *phydev; +}; +#endif diff --git a/drivers/net/qe/dm_qe_uec_phy.c b/drivers/net/qe/dm_qe_uec_phy.c new file mode 100644 index 0000000000..4b5fdc0a06 --- /dev/null +++ b/drivers/net/qe/dm_qe_uec_phy.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * QE UEC ethernet phy controller driver + * + * based on phy parts of drivers/qe/uec.c and drivers/qe/uec_phy.c + * from NXP + * + * Copyright (C) 2020 Heiko Schocher hs@denx.de + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <miiphy.h> +#include <phy.h> +#include <asm/io.h> +#include <linux/ioport.h> + +#include "dm_qe_uec.h" + +struct qe_uec_mdio_priv { + struct ucc_mii_mng *base; +}; + +static int +qe_uec_mdio_read(struct udevice *dev, int addr, int devad, int reg) +{ + struct qe_uec_mdio_priv *priv = dev_get_priv(dev); + struct ucc_mii_mng *regs = priv->base; + u32 tmp_reg; + u16 value; + + debug("%s: regs: %p addr: %x devad: %x reg: %x\n", __func__, regs, + addr, devad, reg); + /* Setting up the MII Mangement Address Register */ + tmp_reg = ((u32) addr << MIIMADD_PHY_ADDRESS_SHIFT) | reg; + out_be32(®s->miimadd, tmp_reg); + + /* clear MII management command cycle */ + out_be32(®s->miimcom, 0); + sync(); + + /* Perform an MII management read cycle */ + out_be32(®s->miimcom, MIIMCOM_READ_CYCLE); + + /* Wait till MII management write is complete */ + while ((in_be32(®s->miimind)) & + (MIIMIND_NOT_VALID | MIIMIND_BUSY)); + + /* Read MII management status */ + value = (u16) in_be32(®s->miimstat); + if (value == 0xffff) + return -EINVAL; + + return value; +}; + +static int +qe_uec_mdio_write(struct udevice *dev, int addr, int devad, int reg, + u16 value) +{ + struct qe_uec_mdio_priv *priv = dev_get_priv(dev); + struct ucc_mii_mng *regs = priv->base; + u32 tmp_reg; + + debug("%s: regs: %p addr: %x devad: %x reg: %x val: %x\n", __func__, + regs, addr, devad, reg, value); + + /* Stop the MII management read cycle */ + out_be32(®s->miimcom, 0); + /* Setting up the MII Mangement Address Register */ + tmp_reg = ((u32) addr << MIIMADD_PHY_ADDRESS_SHIFT) | reg; + out_be32(®s->miimadd, tmp_reg); + + /* Setting up the MII Mangement Control Register with the value */ + out_be32(®s->miimcon, (u32) value); + sync(); + + /* Wait till MII management write is complete */ + while ((in_be32(®s->miimind)) & MIIMIND_BUSY); + + return 0; +}; + +static const struct mdio_ops qe_uec_mdio_ops = { + .read = qe_uec_mdio_read, + .write = qe_uec_mdio_write, +}; + +static int qe_uec_mdio_probe(struct udevice *dev) +{ + struct qe_uec_mdio_priv *priv = dev_get_priv(dev); + fdt_size_t base; + ofnode node; + u32 num = 0; + int ret = -ENODEV; + + priv->base = (struct ucc_mii_mng *)dev_read_addr(dev); + base = (fdt_size_t)priv->base; + + /* + * idea from linux: + * drivers/net/ethernet/freescale/fsl_pq_mdio.c + * + * Find the UCC node that controls the given MDIO node + * + * For some reason, the QE MDIO nodes are not children of the UCC + * devices that control them. Therefore, we need to scan all UCC + * nodes looking for the one that encompases the given MDIO node. + * We do this by comparing physical addresses. The 'start' and + * 'end' addresses of the MDIO node are passed, and the correct + * UCC node will cover the entire address range. + */ + node = ofnode_by_compatible(ofnode_null(), "ucc_geth"); + while (ofnode_valid(node)) { + fdt_size_t size; + fdt_addr_t addr; + + addr = ofnode_get_addr_index(node, 0); + ret = ofnode_get_addr_size_index(node, 0, &size); + + if (addr == FDT_ADDR_T_NONE) { + node = ofnode_by_compatible(node, "ucc_geth"); + continue; + } + + /* check if priv->base in start end */ + if (base > addr && base < (addr + size)) { + ret = ofnode_read_u32(node, "cell-index", &num); + if (ret) + ret = ofnode_read_u32(node, "device-id", + &num); + break; + } + node = ofnode_by_compatible(node, "ucc_geth"); + } + + if (ret) { + printf("%s: no cell-index nor device-id found!", __func__); + return ret; + } + + /* Setup MII master clock source */ + qe_set_mii_clk_src(num - 1); + + return 0; +} + +static const struct udevice_id qe_uec_mdio_ids[] = { + { .compatible = "fsl,ucc-mdio" }, + { } +}; + +U_BOOT_DRIVER(mvmdio) = { + .name = "qe_uec_mdio", + .id = UCLASS_MDIO, + .of_match = qe_uec_mdio_ids, + .probe = qe_uec_mdio_probe, + .ops = &qe_uec_mdio_ops, + .priv_auto_alloc_size = sizeof(struct qe_uec_mdio_priv), +}; diff --git a/drivers/net/qe/uccf.c b/drivers/net/qe/uccf.c new file mode 100644 index 0000000000..9beb5d90ac --- /dev/null +++ b/drivers/net/qe/uccf.c @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu daveliu@freescale.com + * based on source code of Shlomi Gridish + */ + +#include <common.h> +#include <malloc.h> +#include <linux/errno.h> +#include <asm/io.h> +#include <linux/immap_qe.h> +#include "uccf.h" +#include <fsl_qe.h> + +void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf) +{ + out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD); +} + +u32 ucc_fast_get_qe_cr_subblock(int ucc_num) +{ + switch (ucc_num) { + case 0: return QE_CR_SUBBLOCK_UCCFAST1; + case 1: return QE_CR_SUBBLOCK_UCCFAST2; + case 2: return QE_CR_SUBBLOCK_UCCFAST3; + case 3: return QE_CR_SUBBLOCK_UCCFAST4; + case 4: return QE_CR_SUBBLOCK_UCCFAST5; + case 5: return QE_CR_SUBBLOCK_UCCFAST6; + case 6: return QE_CR_SUBBLOCK_UCCFAST7; + case 7: return QE_CR_SUBBLOCK_UCCFAST8; + default: return QE_CR_SUBBLOCK_INVALID; + } +} + +static void ucc_get_cmxucr_reg(int ucc_num, volatile u32 **p_cmxucr, + u8 *reg_num, u8 *shift) +{ + switch (ucc_num) { + case 0: /* UCC1 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr1); + *reg_num = 1; + *shift = 16; + break; + case 2: /* UCC3 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr1); + *reg_num = 1; + *shift = 0; + break; + case 4: /* UCC5 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr2); + *reg_num = 2; + *shift = 16; + break; + case 6: /* UCC7 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr2); + *reg_num = 2; + *shift = 0; + break; + case 1: /* UCC2 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr3); + *reg_num = 3; + *shift = 16; + break; + case 3: /* UCC4 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr3); + *reg_num = 3; + *shift = 0; + break; + case 5: /* UCC6 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr4); + *reg_num = 4; + *shift = 16; + break; + case 7: /* UCC8 */ + *p_cmxucr = &(qe_immr->qmx.cmxucr4); + *reg_num = 4; + *shift = 0; + break; + default: + break; + } +} + +static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode) +{ + volatile u32 *p_cmxucr = NULL; + u8 reg_num = 0; + u8 shift = 0; + u32 clockBits; + u32 clockMask; + int source = -1; + + /* check if the UCC number is in range. */ + if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) + return -EINVAL; + + if (! ((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) { + printf("%s: bad comm mode type passed\n", __FUNCTION__); + return -EINVAL; + } + + ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, ®_num, &shift); + + switch (reg_num) { + case 1: + switch (clock) { + case QE_BRG1: source = 1; break; + case QE_BRG2: source = 2; break; + case QE_BRG7: source = 3; break; + case QE_BRG8: source = 4; break; + case QE_CLK9: source = 5; break; + case QE_CLK10: source = 6; break; + case QE_CLK11: source = 7; break; + case QE_CLK12: source = 8; break; + case QE_CLK15: source = 9; break; + case QE_CLK16: source = 10; break; + default: source = -1; break; + } + break; + case 2: + switch (clock) { + case QE_BRG5: source = 1; break; + case QE_BRG6: source = 2; break; + case QE_BRG7: source = 3; break; + case QE_BRG8: source = 4; break; + case QE_CLK13: source = 5; break; + case QE_CLK14: source = 6; break; + case QE_CLK19: source = 7; break; + case QE_CLK20: source = 8; break; + case QE_CLK15: source = 9; break; + case QE_CLK16: source = 10; break; + default: source = -1; break; + } + break; + case 3: + switch (clock) { + case QE_BRG9: source = 1; break; + case QE_BRG10: source = 2; break; + case QE_BRG15: source = 3; break; + case QE_BRG16: source = 4; break; + case QE_CLK3: source = 5; break; + case QE_CLK4: source = 6; break; + case QE_CLK17: source = 7; break; + case QE_CLK18: source = 8; break; + case QE_CLK7: source = 9; break; + case QE_CLK8: source = 10; break; + case QE_CLK16: source = 11; break; + default: source = -1; break; + } + break; + case 4: + switch (clock) { + case QE_BRG13: source = 1; break; + case QE_BRG14: source = 2; break; + case QE_BRG15: source = 3; break; + case QE_BRG16: source = 4; break; + case QE_CLK5: source = 5; break; + case QE_CLK6: source = 6; break; + case QE_CLK21: source = 7; break; + case QE_CLK22: source = 8; break; + case QE_CLK7: source = 9; break; + case QE_CLK8: source = 10; break; + case QE_CLK16: source = 11; break; + default: source = -1; break; + } + break; + default: + source = -1; + break; + } + + if (source == -1) { + printf("%s: Bad combination of clock and UCC\n", __FUNCTION__); + return -ENOENT; + } + + clockBits = (u32) source; + clockMask = QE_CMXUCR_TX_CLK_SRC_MASK; + if (mode == COMM_DIR_RX) { + clockBits <<= 4; /* Rx field is 4 bits to left of Tx field */ + clockMask <<= 4; /* Rx field is 4 bits to left of Tx field */ + } + clockBits <<= shift; + clockMask <<= shift; + + out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clockMask) | clockBits); + + return 0; +} + +static uint ucc_get_reg_baseaddr(int ucc_num) +{ + uint base = 0; + + /* check if the UCC number is in range */ + if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) { + printf("%s: the UCC num not in ranges\n", __FUNCTION__); + return 0; + } + + switch (ucc_num) { + case 0: base = 0x00002000; break; + case 1: base = 0x00003000; break; + case 2: base = 0x00002200; break; + case 3: base = 0x00003200; break; + case 4: base = 0x00002400; break; + case 5: base = 0x00003400; break; + case 6: base = 0x00002600; break; + case 7: base = 0x00003600; break; + default: break; + } + + base = (uint)qe_immr + base; + return base; +} + +void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode) +{ + ucc_fast_t *uf_regs; + u32 gumr; + + uf_regs = uccf->uf_regs; + + /* Enable reception and/or transmission on this UCC. */ + gumr = in_be32(&uf_regs->gumr); + if (mode & COMM_DIR_TX) { + gumr |= UCC_FAST_GUMR_ENT; + uccf->enabled_tx = 1; + } + if (mode & COMM_DIR_RX) { + gumr |= UCC_FAST_GUMR_ENR; + uccf->enabled_rx = 1; + } + out_be32(&uf_regs->gumr, gumr); +} + +void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode) +{ + ucc_fast_t *uf_regs; + u32 gumr; + + uf_regs = uccf->uf_regs; + + /* Disable reception and/or transmission on this UCC. */ + gumr = in_be32(&uf_regs->gumr); + if (mode & COMM_DIR_TX) { + gumr &= ~UCC_FAST_GUMR_ENT; + uccf->enabled_tx = 0; + } + if (mode & COMM_DIR_RX) { + gumr &= ~UCC_FAST_GUMR_ENR; + uccf->enabled_rx = 0; + } + out_be32(&uf_regs->gumr, gumr); +} + +int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret) +{ + ucc_fast_private_t *uccf; + ucc_fast_t *uf_regs; + + if (!uf_info) + return -EINVAL; + + if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) { + printf("%s: Illagal UCC number!\n", __FUNCTION__); + return -EINVAL; + } + + uccf = (ucc_fast_private_t *)malloc(sizeof(ucc_fast_private_t)); + if (!uccf) { + printf("%s: No memory for UCC fast data structure!\n", + __FUNCTION__); + return -ENOMEM; + } + memset(uccf, 0, sizeof(ucc_fast_private_t)); + + /* Save fast UCC structure */ + uccf->uf_info = uf_info; + uccf->uf_regs = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num); + + if (uccf->uf_regs == NULL) { + printf("%s: No memory map for UCC fast controller!\n", + __FUNCTION__); + return -ENOMEM; + } + + uccf->enabled_tx = 0; + uccf->enabled_rx = 0; + + uf_regs = uccf->uf_regs; + uccf->p_ucce = (u32 *) &(uf_regs->ucce); + uccf->p_uccm = (u32 *) &(uf_regs->uccm); + + /* Init GUEMR register, UCC both Rx and Tx is Fast protocol */ + out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX + | UCC_GUEMR_MODE_FAST_TX); + + /* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */ + out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH); + + /* Set the Giga ethernet VFIFO stuff */ + if (uf_info->eth_type == GIGA_ETH) { + /* Allocate memory for Tx Virtual Fifo */ + uccf->ucc_fast_tx_virtual_fifo_base_offset = + qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT, + UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); + + /* Allocate memory for Rx Virtual Fifo */ + uccf->ucc_fast_rx_virtual_fifo_base_offset = + qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT + + UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD, + UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); + + /* utfb, urfb are offsets from MURAM base */ + out_be32(&uf_regs->utfb, + uccf->ucc_fast_tx_virtual_fifo_base_offset); + out_be32(&uf_regs->urfb, + uccf->ucc_fast_rx_virtual_fifo_base_offset); + + /* Set Virtual Fifo registers */ + out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT); + out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT); + out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT); + out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT); + out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT); + out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT); + } + + /* Set the Fast ethernet VFIFO stuff */ + if (uf_info->eth_type == FAST_ETH) { + /* Allocate memory for Tx Virtual Fifo */ + uccf->ucc_fast_tx_virtual_fifo_base_offset = + qe_muram_alloc(UCC_GETH_UTFS_INIT, + UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); + + /* Allocate memory for Rx Virtual Fifo */ + uccf->ucc_fast_rx_virtual_fifo_base_offset = + qe_muram_alloc(UCC_GETH_URFS_INIT + + UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD, + UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); + + /* utfb, urfb are offsets from MURAM base */ + out_be32(&uf_regs->utfb, + uccf->ucc_fast_tx_virtual_fifo_base_offset); + out_be32(&uf_regs->urfb, + uccf->ucc_fast_rx_virtual_fifo_base_offset); + + /* Set Virtual Fifo registers */ + out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT); + out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT); + out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT); + out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT); + out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT); + out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT); + } + + /* Rx clock routing */ + if (uf_info->rx_clock != QE_CLK_NONE) { + if (ucc_set_clk_src(uf_info->ucc_num, + uf_info->rx_clock, COMM_DIR_RX)) { + printf("%s: Illegal value for parameter 'RxClock'.\n", + __FUNCTION__); + return -EINVAL; + } + } + + /* Tx clock routing */ + if (uf_info->tx_clock != QE_CLK_NONE) { + if (ucc_set_clk_src(uf_info->ucc_num, + uf_info->tx_clock, COMM_DIR_TX)) { + printf("%s: Illegal value for parameter 'TxClock'.\n", + __FUNCTION__); + return -EINVAL; + } + } + + /* Clear interrupt mask register to disable all of interrupts */ + out_be32(&uf_regs->uccm, 0x0); + + /* Writing '1' to clear all of envents */ + out_be32(&uf_regs->ucce, 0xffffffff); + + *uccf_ret = uccf; + return 0; +} diff --git a/drivers/net/qe/uccf.h b/drivers/net/qe/uccf.h new file mode 100644 index 0000000000..4098c66317 --- /dev/null +++ b/drivers/net/qe/uccf.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu daveliu@freescale.com + * based on source code of Shlomi Gridish + */ + +#ifndef __UCCF_H__ +#define __UCCF_H__ + +#include "common.h" +#include "linux/immap_qe.h" +#include <fsl_qe.h> + +/* Fast or Giga ethernet +*/ +typedef enum enet_type { + FAST_ETH, + GIGA_ETH, +} enet_type_e; + +/* General UCC Extended Mode Register +*/ +#define UCC_GUEMR_MODE_MASK_RX 0x02 +#define UCC_GUEMR_MODE_MASK_TX 0x01 +#define UCC_GUEMR_MODE_FAST_RX 0x02 +#define UCC_GUEMR_MODE_FAST_TX 0x01 +#define UCC_GUEMR_MODE_SLOW_RX 0x00 +#define UCC_GUEMR_MODE_SLOW_TX 0x00 +#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 must be set 1 */ + +/* General UCC FAST Mode Register +*/ +#define UCC_FAST_GUMR_TCI 0x20000000 +#define UCC_FAST_GUMR_TRX 0x10000000 +#define UCC_FAST_GUMR_TTX 0x08000000 +#define UCC_FAST_GUMR_CDP 0x04000000 +#define UCC_FAST_GUMR_CTSP 0x02000000 +#define UCC_FAST_GUMR_CDS 0x01000000 +#define UCC_FAST_GUMR_CTSS 0x00800000 +#define UCC_FAST_GUMR_TXSY 0x00020000 +#define UCC_FAST_GUMR_RSYN 0x00010000 +#define UCC_FAST_GUMR_RTSM 0x00002000 +#define UCC_FAST_GUMR_REVD 0x00000400 +#define UCC_FAST_GUMR_ENR 0x00000020 +#define UCC_FAST_GUMR_ENT 0x00000010 + +/* GUMR [MODE] bit maps +*/ +#define UCC_FAST_GUMR_HDLC 0x00000000 +#define UCC_FAST_GUMR_QMC 0x00000002 +#define UCC_FAST_GUMR_UART 0x00000004 +#define UCC_FAST_GUMR_BISYNC 0x00000008 +#define UCC_FAST_GUMR_ATM 0x0000000a +#define UCC_FAST_GUMR_ETH 0x0000000c + +/* Transmit On Demand (UTORD) +*/ +#define UCC_SLOW_TOD 0x8000 +#define UCC_FAST_TOD 0x8000 + +/* Fast Ethernet (10/100 Mbps) +*/ +#define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size */ +#define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */ +#define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */ +#define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size */ +#define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */ +#define UCC_GETH_UTFTT_INIT 128 + +/* Gigabit Ethernet (1000 Mbps) +*/ +#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual FIFO size */ +#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */ +#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */ +#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual FIFO size */ +#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */ +#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */ + +/* UCC fast alignment +*/ +#define UCC_FAST_RX_ALIGN 4 +#define UCC_FAST_MRBLR_ALIGNMENT 4 +#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8 + +/* Sizes +*/ +#define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD 8 + +/* UCC fast structure. +*/ +typedef struct ucc_fast_info { + int ucc_num; + qe_clock_e rx_clock; + qe_clock_e tx_clock; + enet_type_e eth_type; +} ucc_fast_info_t; + +typedef struct ucc_fast_private { + ucc_fast_info_t *uf_info; + ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs */ + u32 *p_ucce; /* a pointer to the event register */ + u32 *p_uccm; /* a pointer to the mask register */ + int enabled_tx; /* whether UCC is enabled for Tx (ENT) */ + int enabled_rx; /* whether UCC is enabled for Rx (ENR) */ + u32 ucc_fast_tx_virtual_fifo_base_offset; + u32 ucc_fast_rx_virtual_fifo_base_offset; +} ucc_fast_private_t; + +void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf); +u32 ucc_fast_get_qe_cr_subblock(int ucc_num); +void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode); +void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode); +int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret); + +#endif /* __UCCF_H__ */ diff --git a/drivers/net/qe/uec.h b/drivers/net/qe/uec.h new file mode 100644 index 0000000000..ada3ac5fd7 --- /dev/null +++ b/drivers/net/qe/uec.h @@ -0,0 +1,742 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. + * + * Dave Liu daveliu@freescale.com + * based on source code of Shlomi Gridish + */ + +#ifndef __UEC_H__ +#define __UEC_H__ + +#include "uccf.h" +#include <fsl_qe.h> +#include <phy.h> + +#define MAX_TX_THREADS 8 +#define MAX_RX_THREADS 8 +#define MAX_TX_QUEUES 8 +#define MAX_RX_QUEUES 8 +#define MAX_PREFETCHED_BDS 4 +#define MAX_IPH_OFFSET_ENTRY 8 +#define MAX_ENET_INIT_PARAM_ENTRIES_RX 9 +#define MAX_ENET_INIT_PARAM_ENTRIES_TX 8 + +/* UEC UPSMR (Protocol Specific Mode Register) + */ +#define UPSMR_ECM 0x04000000 /* Enable CAM Miss */ +#define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */ +#define UPSMR_PRO 0x00400000 /* Promiscuous */ +#define UPSMR_CAP 0x00200000 /* CAM polarity */ +#define UPSMR_RSH 0x00100000 /* Receive Short Frames */ +#define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */ +#define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */ +#define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */ +#define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */ +#define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */ +#define UPSMR_CAM 0x00000400 /* CAM Address Matching */ +#define UPSMR_BRO 0x00000200 /* Broadcast Address */ +#define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */ +#define UPSMR_SGMM 0x00000020 /* SGMII mode */ + +#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1) + +/* UEC MACCFG1 (MAC Configuration 1 Register) + */ +#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */ +#define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */ +#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */ +#define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */ +#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */ +#define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */ + +#define MACCFG1_INIT_VALUE (0) + +/* UEC MACCFG2 (MAC Configuration 2 Register) + */ +#define MACCFG2_PREL 0x00007000 +#define MACCFG2_PREL_SHIFT (31 - 19) +#define MACCFG2_PREL_MASK 0x0000f000 +#define MACCFG2_SRP 0x00000080 +#define MACCFG2_STP 0x00000040 +#define MACCFG2_RESERVED_1 0x00000020 /* must be set */ +#define MACCFG2_LC 0x00000010 /* Length Check */ +#define MACCFG2_MPE 0x00000008 +#define MACCFG2_FDX 0x00000001 /* Full Duplex */ +#define MACCFG2_FDX_MASK 0x00000001 +#define MACCFG2_PAD_CRC 0x00000004 +#define MACCFG2_CRC_EN 0x00000002 +#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 +#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 +#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004 +#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 +#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 +#define MACCFG2_INTERFACE_MODE_MASK 0x00000300 + +#define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \ + MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX) + +/* UEC Event Register +*/ +#define UCCE_MPD 0x80000000 +#define UCCE_SCAR 0x40000000 +#define UCCE_GRA 0x20000000 +#define UCCE_CBPR 0x10000000 +#define UCCE_BSY 0x08000000 +#define UCCE_RXC 0x04000000 +#define UCCE_TXC 0x02000000 +#define UCCE_TXE 0x01000000 +#define UCCE_TXB7 0x00800000 +#define UCCE_TXB6 0x00400000 +#define UCCE_TXB5 0x00200000 +#define UCCE_TXB4 0x00100000 +#define UCCE_TXB3 0x00080000 +#define UCCE_TXB2 0x00040000 +#define UCCE_TXB1 0x00020000 +#define UCCE_TXB0 0x00010000 +#define UCCE_RXB7 0x00008000 +#define UCCE_RXB6 0x00004000 +#define UCCE_RXB5 0x00002000 +#define UCCE_RXB4 0x00001000 +#define UCCE_RXB3 0x00000800 +#define UCCE_RXB2 0x00000400 +#define UCCE_RXB1 0x00000200 +#define UCCE_RXB0 0x00000100 +#define UCCE_RXF7 0x00000080 +#define UCCE_RXF6 0x00000040 +#define UCCE_RXF5 0x00000020 +#define UCCE_RXF4 0x00000010 +#define UCCE_RXF3 0x00000008 +#define UCCE_RXF2 0x00000004 +#define UCCE_RXF1 0x00000002 +#define UCCE_RXF0 0x00000001 + +#define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \ + UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0) +#define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \ + UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0) +#define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \ + UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0) +#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \ + UCCE_RXC | UCCE_TXC | UCCE_TXE) + +/* UEC TEMODR Register +*/ +#define TEMODER_SCHEDULER_ENABLE 0x2000 +#define TEMODER_IP_CHECKSUM_GENERATE 0x0400 +#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 +#define TEMODER_RMON_STATISTICS 0x0100 +#define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) + +#define TEMODER_INIT_VALUE 0xc000 + +/* UEC REMODR Register +*/ +#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 +#define REMODER_RX_EXTENDED_FEATURES 0x80000000 +#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) +#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) +#define REMODER_RX_QOS_MODE_SHIFT (31-15) +#define REMODER_RMON_STATISTICS 0x00001000 +#define REMODER_RX_EXTENDED_FILTERING 0x00000800 +#define REMODER_NUM_OF_QUEUES_SHIFT (31-23) +#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 +#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 +#define REMODER_IP_CHECKSUM_CHECK 0x00000002 +#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 + +#define REMODER_INIT_VALUE 0 + +/* BMRx - Bus Mode Register */ +#define BMR_GLB 0x20 +#define BMR_BO_BE 0x10 +#define BMR_DTB_SECONDARY_BUS 0x02 +#define BMR_BDB_SECONDARY_BUS 0x01 + +#define BMR_SHIFT 24 +#define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE) + +/* UEC UCCS (Ethernet Status Register) + */ +#define UCCS_BPR 0x02 +#define UCCS_PAU 0x02 +#define UCCS_MPD 0x01 + +/* UEC MIIMCFG (MII Management Configuration Register) + */ +#define MIIMCFG_RESET_MANAGEMENT 0x80000000 +#define MIIMCFG_NO_PREAMBLE 0x00000010 +#define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31) +#define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f +#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001 +#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002 +#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003 +#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004 +#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005 +#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006 +#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007 + +#define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \ + MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 + +/* UEC MIIMCOM (MII Management Command Register) + */ +#define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */ +#define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */ + +/* UEC MIIMADD (MII Management Address Register) + */ +#define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23) +#define MIIMADD_PHY_REGISTER_SHIFT (31 - 31) + +/* UEC MIIMCON (MII Management Control Register) + */ +#define MIIMCON_PHY_CONTROL_SHIFT (31 - 31) +#define MIIMCON_PHY_STATUS_SHIFT (31 - 31) + +/* UEC MIIMIND (MII Management Indicator Register) + */ +#define MIIMIND_NOT_VALID 0x00000004 +#define MIIMIND_SCAN 0x00000002 +#define MIIMIND_BUSY 0x00000001 + +/* UEC UTBIPAR (Ten Bit Interface Physical Address Register) + */ +#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) +#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f + +/* UEC UESCR (Ethernet Statistics Control Register) + */ +#define UESCR_AUTOZ 0x8000 +#define UESCR_CLRCNT 0x4000 +#define UESCR_MAXCOV_SHIFT (15 - 7) +#define UESCR_SCOV_SHIFT (15 - 15) + +/****** Tx data struct collection ******/ +/* Tx thread data, each Tx thread has one this struct. +*/ +typedef struct uec_thread_data_tx { + u8 res0[136]; +} __attribute__ ((packed)) uec_thread_data_tx_t; + +/* Tx thread parameter, each Tx thread has one this struct. +*/ +typedef struct uec_thread_tx_pram { + u8 res0[64]; +} __attribute__ ((packed)) uec_thread_tx_pram_t; + +/* Send queue queue-descriptor, each Tx queue has one this QD +*/ +typedef struct uec_send_queue_qd { + u32 bd_ring_base; /* pointer to BD ring base address */ + u8 res0[0x8]; + u32 last_bd_completed_address; /* last entry in BD ring */ + u8 res1[0x30]; +} __attribute__ ((packed)) uec_send_queue_qd_t; + +/* Send queue memory region */ +typedef struct uec_send_queue_mem_region { + uec_send_queue_qd_t sqqd[MAX_TX_QUEUES]; +} __attribute__ ((packed)) uec_send_queue_mem_region_t; + +/* Scheduler struct +*/ +typedef struct uec_scheduler { + u16 cpucount0; /* CPU packet counter */ + u16 cpucount1; /* CPU packet counter */ + u16 cecount0; /* QE packet counter */ + u16 cecount1; /* QE packet counter */ + u16 cpucount2; /* CPU packet counter */ + u16 cpucount3; /* CPU packet counter */ + u16 cecount2; /* QE packet counter */ + u16 cecount3; /* QE packet counter */ + u16 cpucount4; /* CPU packet counter */ + u16 cpucount5; /* CPU packet counter */ + u16 cecount4; /* QE packet counter */ + u16 cecount5; /* QE packet counter */ + u16 cpucount6; /* CPU packet counter */ + u16 cpucount7; /* CPU packet counter */ + u16 cecount6; /* QE packet counter */ + u16 cecount7; /* QE packet counter */ + u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */ + u32 rtsrshadow; /* temporary variable handled by QE */ + u32 time; /* temporary variable handled by QE */ + u32 ttl; /* temporary variable handled by QE */ + u32 mblinterval; /* max burst length interval */ + u16 nortsrbytetime; /* normalized value of byte time in tsr units */ + u8 fracsiz; + u8 res0[1]; + u8 strictpriorityq; /* Strict Priority Mask register */ + u8 txasap; /* Transmit ASAP register */ + u8 extrabw; /* Extra BandWidth register */ + u8 oldwfqmask; /* temporary variable handled by QE */ + u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */ + u32 minw; /* temporary variable handled by QE */ + u8 res1[0x70-0x64]; +} __attribute__ ((packed)) uec_scheduler_t; + +/* Tx firmware counters +*/ +typedef struct uec_tx_firmware_statistics_pram { + u32 sicoltx; /* single collision */ + u32 mulcoltx; /* multiple collision */ + u32 latecoltxfr; /* late collision */ + u32 frabortduecol; /* frames aborted due to tx collision */ + u32 frlostinmactxer; /* frames lost due to internal MAC error tx */ + u32 carriersenseertx; /* carrier sense error */ + u32 frtxok; /* frames transmitted OK */ + u32 txfrexcessivedefer; + u32 txpkts256; /* total packets(including bad) 256~511 B */ + u32 txpkts512; /* total packets(including bad) 512~1023B */ + u32 txpkts1024; /* total packets(including bad) 1024~1518B */ + u32 txpktsjumbo; /* total packets(including bad) >1024 */ +} __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t; + +/* Tx global parameter table +*/ +typedef struct uec_tx_global_pram { + u16 temoder; + u8 res0[0x38-0x02]; + u32 sqptr; + u32 schedulerbasepointer; + u32 txrmonbaseptr; + u32 tstate; + u8 iphoffset[MAX_IPH_OFFSET_ENTRY]; + u32 vtagtable[0x8]; + u32 tqptr; + u8 res2[0x80-0x74]; +} __attribute__ ((packed)) uec_tx_global_pram_t; + + +/****** Rx data struct collection ******/ +/* Rx thread data, each Rx thread has one this struct. +*/ +typedef struct uec_thread_data_rx { + u8 res0[40]; +} __attribute__ ((packed)) uec_thread_data_rx_t; + +/* Rx thread parameter, each Rx thread has one this struct. +*/ +typedef struct uec_thread_rx_pram { + u8 res0[128]; +} __attribute__ ((packed)) uec_thread_rx_pram_t; + +/* Rx firmware counters +*/ +typedef struct uec_rx_firmware_statistics_pram { + u32 frrxfcser; /* frames with crc error */ + u32 fraligner; /* frames with alignment error */ + u32 inrangelenrxer; /* in range length error */ + u32 outrangelenrxer; /* out of range length error */ + u32 frtoolong; /* frame too long */ + u32 runt; /* runt */ + u32 verylongevent; /* very long event */ + u32 symbolerror; /* symbol error */ + u32 dropbsy; /* drop because of BD not ready */ + u8 res0[0x8]; + u32 mismatchdrop; /* drop because of MAC filtering */ + u32 underpkts; /* total frames less than 64 octets */ + u32 pkts256; /* total frames(including bad)256~511 B */ + u32 pkts512; /* total frames(including bad)512~1023 B */ + u32 pkts1024; /* total frames(including bad)1024~1518 B */ + u32 pktsjumbo; /* total frames(including bad) >1024 B */ + u32 frlossinmacer; + u32 pausefr; /* pause frames */ + u8 res1[0x4]; + u32 removevlan; + u32 replacevlan; + u32 insertvlan; +} __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t; + +/* Rx interrupt coalescing entry, each Rx queue has one this entry. +*/ +typedef struct uec_rx_interrupt_coalescing_entry { + u32 maxvalue; + u32 counter; +} __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t; + +typedef struct uec_rx_interrupt_coalescing_table { + uec_rx_interrupt_coalescing_entry_t entry[MAX_RX_QUEUES]; +} __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t; + +/* RxBD queue entry, each Rx queue has one this entry. +*/ +typedef struct uec_rx_bd_queues_entry { + u32 bdbaseptr; /* BD base pointer */ + u32 bdptr; /* BD pointer */ + u32 externalbdbaseptr; /* external BD base pointer */ + u32 externalbdptr; /* external BD pointer */ +} __attribute__ ((packed)) uec_rx_bd_queues_entry_t; + +/* Rx global paramter table +*/ +typedef struct uec_rx_global_pram { + u32 remoder; /* ethernet mode reg. */ + u32 rqptr; /* base pointer to the Rx Queues */ + u32 res0[0x1]; + u8 res1[0x20-0xC]; + u16 typeorlen; + u8 res2[0x1]; + u8 rxgstpack; /* ack on GRACEFUL STOP RX command */ + u32 rxrmonbaseptr; /* Rx RMON statistics base */ + u8 res3[0x30-0x28]; + u32 intcoalescingptr; /* Interrupt coalescing table pointer */ + u8 res4[0x36-0x34]; + u8 rstate; + u8 res5[0x46-0x37]; + u16 mrblr; /* max receive buffer length reg. */ + u32 rbdqptr; /* RxBD parameter table description */ + u16 mflr; /* max frame length reg. */ + u16 minflr; /* min frame length reg. */ + u16 maxd1; /* max dma1 length reg. */ + u16 maxd2; /* max dma2 length reg. */ + u32 ecamptr; /* external CAM address */ + u32 l2qt; /* VLAN priority mapping table. */ + u32 l3qt[0x8]; /* IP priority mapping table. */ + u16 vlantype; /* vlan type */ + u16 vlantci; /* default vlan tci */ + u8 addressfiltering[64];/* address filtering data structure */ + u32 exfGlobalParam; /* extended filtering global parameters */ + u8 res6[0x100-0xC4]; /* Initialize to zero */ +} __attribute__ ((packed)) uec_rx_global_pram_t; + +#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01 + + +/****** UEC common ******/ +/* UCC statistics - hardware counters +*/ +typedef struct uec_hardware_statistics { + u32 tx64; + u32 tx127; + u32 tx255; + u32 rx64; + u32 rx127; + u32 rx255; + u32 txok; + u16 txcf; + u32 tmca; + u32 tbca; + u32 rxfok; + u32 rxbok; + u32 rbyt; + u32 rmca; + u32 rbca; +} __attribute__ ((packed)) uec_hardware_statistics_t; + +/* InitEnet command parameter +*/ +typedef struct uec_init_cmd_pram { + u8 resinit0; + u8 resinit1; + u8 resinit2; + u8 resinit3; + u16 resinit4; + u8 res1[0x1]; + u8 largestexternallookupkeysize; + u32 rgftgfrxglobal; + u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */ + u8 res2[0x38 - 0x30]; + u32 txglobal; /* tx global */ + u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */ + u8 res3[0x1]; +} __attribute__ ((packed)) uec_init_cmd_pram_t; + +#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4) +#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8) + +#define ENET_INIT_PARAM_RISC_MASK 0x0000003f +#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0 +#define ENET_INIT_PARAM_SNUM_MASK 0xff000000 +#define ENET_INIT_PARAM_SNUM_SHIFT 24 + +#define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06 +#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30 +#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff +#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00 +#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400 + +/* structure representing 82xx Address Filtering Enet Address in PRAM +*/ +typedef struct uec_82xx_enet_address { + u8 res1[0x2]; + u16 h; /* address (MSB) */ + u16 m; /* address */ + u16 l; /* address (LSB) */ +} __attribute__ ((packed)) uec_82xx_enet_address_t; + +/* structure representing 82xx Address Filtering PRAM +*/ +typedef struct uec_82xx_address_filtering_pram { + u32 iaddr_h; /* individual address filter, high */ + u32 iaddr_l; /* individual address filter, low */ + u32 gaddr_h; /* group address filter, high */ + u32 gaddr_l; /* group address filter, low */ + uec_82xx_enet_address_t taddr; + uec_82xx_enet_address_t paddr[4]; + u8 res0[0x40-0x38]; +} __attribute__ ((packed)) uec_82xx_address_filtering_pram_t; + +/* Buffer Descriptor +*/ +typedef struct buffer_descriptor { + u16 status; + u16 len; + u32 data; +} __attribute__ ((packed)) qe_bd_t, *p_bd_t; + +#define SIZEOFBD sizeof(qe_bd_t) + +/* Common BD flags +*/ +#define BD_WRAP 0x2000 +#define BD_INT 0x1000 +#define BD_LAST 0x0800 +#define BD_CLEAN 0x3000 + +/* TxBD status flags +*/ +#define TxBD_READY 0x8000 +#define TxBD_PADCRC 0x4000 +#define TxBD_WRAP BD_WRAP +#define TxBD_INT BD_INT +#define TxBD_LAST BD_LAST +#define TxBD_TXCRC 0x0400 +#define TxBD_DEF 0x0200 +#define TxBD_PP 0x0100 +#define TxBD_LC 0x0080 +#define TxBD_RL 0x0040 +#define TxBD_RC 0x003C +#define TxBD_UNDERRUN 0x0002 +#define TxBD_TRUNC 0x0001 + +#define TxBD_ERROR (TxBD_UNDERRUN | TxBD_TRUNC) + +/* RxBD status flags +*/ +#define RxBD_EMPTY 0x8000 +#define RxBD_OWNER 0x4000 +#define RxBD_WRAP BD_WRAP +#define RxBD_INT BD_INT +#define RxBD_LAST BD_LAST +#define RxBD_FIRST 0x0400 +#define RxBD_CMR 0x0200 +#define RxBD_MISS 0x0100 +#define RxBD_BCAST 0x0080 +#define RxBD_MCAST 0x0040 +#define RxBD_LG 0x0020 +#define RxBD_NO 0x0010 +#define RxBD_SHORT 0x0008 +#define RxBD_CRCERR 0x0004 +#define RxBD_OVERRUN 0x0002 +#define RxBD_IPCH 0x0001 + +#define RxBD_ERROR (RxBD_LG | RxBD_NO | RxBD_SHORT | \ + RxBD_CRCERR | RxBD_OVERRUN) + +/* BD access macros +*/ +#define BD_STATUS(_bd) (((p_bd_t)(_bd))->status) +#define BD_STATUS_SET(_bd, _val) (((p_bd_t)(_bd))->status = _val) +#define BD_LENGTH(_bd) (((p_bd_t)(_bd))->len) +#define BD_LENGTH_SET(_bd, _val) (((p_bd_t)(_bd))->len = _val) +#define BD_DATA_CLEAR(_bd) (((p_bd_t)(_bd))->data = 0) +#define BD_IS_DATA(_bd) (((p_bd_t)(_bd))->data) +#define BD_DATA(_bd) ((u8 *)(((p_bd_t)(_bd))->data)) +#define BD_DATA_SET(_bd, _data) (((p_bd_t)(_bd))->data = (u32)(_data)) +#define BD_ADVANCE(_bd,_status,_base) \ + (((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd)) + +/* Rx Prefetched BDs +*/ +typedef struct uec_rx_prefetched_bds { + qe_bd_t bd[MAX_PREFETCHED_BDS]; /* prefetched bd */ +} __attribute__ ((packed)) uec_rx_prefetched_bds_t; + +/* Alignments + */ +#define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64 +#define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64 +#define UEC_THREAD_RX_PRAM_ALIGNMENT 128 +#define UEC_THREAD_TX_PRAM_ALIGNMENT 64 +#define UEC_THREAD_DATA_ALIGNMENT 256 +#define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32 +#define UEC_SCHEDULER_ALIGNMENT 4 +#define UEC_TX_STATISTICS_ALIGNMENT 4 +#define UEC_RX_STATISTICS_ALIGNMENT 4 +#define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4 +#define UEC_RX_BD_QUEUES_ALIGNMENT 8 +#define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128 +#define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 +#define UEC_RX_BD_RING_ALIGNMENT 32 +#define UEC_TX_BD_RING_ALIGNMENT 32 +#define UEC_MRBLR_ALIGNMENT 128 +#define UEC_RX_BD_RING_SIZE_ALIGNMENT 4 +#define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32 +#define UEC_RX_DATA_BUF_ALIGNMENT 64 + +#define UEC_VLAN_PRIORITY_MAX 8 +#define UEC_IP_PRIORITY_MAX 64 +#define UEC_TX_VTAG_TABLE_ENTRY_MAX 8 +#define UEC_RX_BD_RING_SIZE_MIN 8 +#define UEC_TX_BD_RING_SIZE_MIN 2 + +/* Ethernet speed +*/ +typedef enum enet_speed { + ENET_SPEED_10BT, /* 10 Base T */ + ENET_SPEED_100BT, /* 100 Base T */ + ENET_SPEED_1000BT /* 1000 Base T */ +} enet_speed_e; + +/* Ethernet Address Type. +*/ +typedef enum enet_addr_type { + ENET_ADDR_TYPE_INDIVIDUAL, + ENET_ADDR_TYPE_GROUP, + ENET_ADDR_TYPE_BROADCAST +} enet_addr_type_e; + +/* TBI / MII Set Register +*/ +typedef enum enet_tbi_mii_reg { + ENET_TBI_MII_CR = 0x00, + ENET_TBI_MII_SR = 0x01, + ENET_TBI_MII_ANA = 0x04, + ENET_TBI_MII_ANLPBPA = 0x05, + ENET_TBI_MII_ANEX = 0x06, + ENET_TBI_MII_ANNPT = 0x07, + ENET_TBI_MII_ANLPANP = 0x08, + ENET_TBI_MII_EXST = 0x0F, + ENET_TBI_MII_JD = 0x10, + ENET_TBI_MII_TBICON = 0x11 +} enet_tbi_mii_reg_e; + +/* TBI MDIO register bit fields*/ +#define TBICON_CLK_SELECT 0x0020 +#define TBIANA_ASYMMETRIC_PAUSE 0x0100 +#define TBIANA_SYMMETRIC_PAUSE 0x0080 +#define TBIANA_HALF_DUPLEX 0x0040 +#define TBIANA_FULL_DUPLEX 0x0020 +#define TBICR_PHY_RESET 0x8000 +#define TBICR_ANEG_ENABLE 0x1000 +#define TBICR_RESTART_ANEG 0x0200 +#define TBICR_FULL_DUPLEX 0x0100 +#define TBICR_SPEED1_SET 0x0040 + +#define TBIANA_SETTINGS ( \ + TBIANA_ASYMMETRIC_PAUSE \ + | TBIANA_SYMMETRIC_PAUSE \ + | TBIANA_FULL_DUPLEX \ + ) + +#define TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + +/* UEC number of threads +*/ +typedef enum uec_num_of_threads { + UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */ + UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */ + UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */ + UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */ + UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */ +} uec_num_of_threads_e; + +/* UEC initialization info struct +*/ +#define STD_UEC_INFO(num) \ +{ \ + .uf_info = { \ + .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\ + .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \ + .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \ + .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\ + }, \ + .num_threads_tx = UEC_NUM_OF_THREADS_1, \ + .num_threads_rx = UEC_NUM_OF_THREADS_1, \ + .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ + .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ + .tx_bd_ring_len = 16, \ + .rx_bd_ring_len = 16, \ + .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \ + .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \ + .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \ +} + +typedef struct uec_info { + ucc_fast_info_t uf_info; + uec_num_of_threads_e num_threads_tx; + uec_num_of_threads_e num_threads_rx; + unsigned int risc_tx; + unsigned int risc_rx; + u16 rx_bd_ring_len; + u16 tx_bd_ring_len; + u8 phy_address; + phy_interface_t enet_interface_type; + int speed; +} uec_info_t; + +/* UEC driver initialized info +*/ +#define MAX_RXBUF_LEN 1536 +#define MAX_FRAME_LEN 1518 +#define MIN_FRAME_LEN 64 +#define MAX_DMA1_LEN 1520 +#define MAX_DMA2_LEN 1520 + +/* UEC driver private struct +*/ +typedef struct uec_private { + uec_info_t *uec_info; + ucc_fast_private_t *uccf; + struct eth_device *dev; + uec_t *uec_regs; + /* enet init command parameter */ + uec_init_cmd_pram_t *p_init_enet_param; + u32 init_enet_param_offset; + /* Rx and Tx paramter */ + uec_rx_global_pram_t *p_rx_glbl_pram; + u32 rx_glbl_pram_offset; + uec_tx_global_pram_t *p_tx_glbl_pram; + u32 tx_glbl_pram_offset; + uec_send_queue_mem_region_t *p_send_q_mem_reg; + u32 send_q_mem_reg_offset; + uec_thread_data_tx_t *p_thread_data_tx; + u32 thread_dat_tx_offset; + uec_thread_data_rx_t *p_thread_data_rx; + u32 thread_dat_rx_offset; + uec_rx_bd_queues_entry_t *p_rx_bd_qs_tbl; + u32 rx_bd_qs_tbl_offset; + /* BDs specific */ + u8 *p_tx_bd_ring; + u32 tx_bd_ring_offset; + u8 *p_rx_bd_ring; + u32 rx_bd_ring_offset; + u8 *p_rx_buf; + u32 rx_buf_offset; + volatile qe_bd_t *txBd; + volatile qe_bd_t *rxBd; + /* Status */ + int mac_tx_enabled; + int mac_rx_enabled; + int grace_stopped_tx; + int grace_stopped_rx; + int the_first_run; +#if !defined(COFIG_DM) + /* PHY specific */ + struct uec_mii_info *mii_info; + int oldspeed; + int oldduplex; + int oldlink; +#endif +} uec_private_t; + +int uec_initialize(bd_t *bis, uec_info_t *uec_info); +int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num); +int uec_standard_init(bd_t *bis); +#endif /* __UEC_H__ */ diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c index 9beb5d90ac..41cf54b488 100644 --- a/drivers/qe/uccf.c +++ b/drivers/qe/uccf.c @@ -14,6 +14,7 @@ #include "uccf.h" #include <fsl_qe.h>
+#if !defined(CONFIG_DM_ETH) void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf) { out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD); @@ -386,3 +387,4 @@ int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret) *uccf_ret = uccf; return 0; } +#endif diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 69cdf9444a..ccae3d9ce4 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -18,6 +18,7 @@ #include <fsl_qe.h> #include <phy.h>
+#if !defined(CONFIG_DM_ETH) /* Default UTBIPAR SMI address */ #ifndef CONFIG_UTBIPAR_INIT_TBIPA #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F @@ -1428,3 +1429,4 @@ int uec_standard_init(bd_t *bis) { return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info)); } +#endif diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 9425379794..02198fb6db 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -22,6 +22,8 @@ #include <fsl_qe.h> #include <phy.h>
+#if !defined(CONFIG_DM_ETH) + #define ugphy_printk(format, arg...) \ printf(format "\n", ## arg)
@@ -909,3 +911,4 @@ void change_phy_interface_mode (struct eth_device *dev, marvell_phy_interface_mode (dev, type, speed); #endif } +#endif