On Tuesday, December 01, 2015 at 05:48:34 PM, dinguyen@opensource.altera.com wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
Add miscellaneous functions(arch_early_init_r, print_cpuinfo, overwrite_console, enable_caches, and cpu_mmc_init). Also, the Arria10 has a firewall protection around the SDRAM and OCRAM. These firewalls are to be disabled in order for U-Boot to function.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
v2: reuse misc functions from a5/c5
arch/arm/mach-socfpga/misc.c | 56 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 54 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index bbd31ef..f8aca55 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -15,6 +15,7 @@ #include <watchdog.h> #include <asm/arch/reset_manager.h> #include <asm/arch/scan_manager.h> +#include <asm/arch/sdram_a10.h> #include <asm/arch/system_manager.h> #include <asm/arch/dwmmc.h> #include <asm/arch/nic301.h> @@ -31,11 +32,16 @@ static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; static struct socfpga_reset_manager *reset_manager_base = (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; -static struct nic301_registers *nic301_regs =
- (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
For the sake of consistency, I'd just ifdef this with ifdef CV || AV and the socfpga_noc stuff with ifdef A10 instead of moving things around this way.
static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
- (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
- (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+#endif
int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); @@ -218,10 +224,14 @@ static int socfpga_fpga_id(const bool print_id) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
- puts("CPU : Altera SOCFPGA Arria 10 Platform\n");
No FPGA type detection happens on A10 ? :) Also, CPU is not "Arria 10 platform", CPU is still Altera SoCFPGA or possibly Altera SoCFPGA Arria 10 , right ?
+#else const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; puts("CPU: Altera SoCFPGA Platform\n"); socfpga_fpga_id(1); printf("BOOT: %s\n", bsel_str[bsel].name); +#endif return 0; } #endif @@ -303,6 +313,47 @@ int arch_cpu_init(void) return 0; }
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +/*
- This function initializes security policies to be consistent across
- all logic units in the Arria 10.
- The idea is to set all security policies to be normal, nonsecure
- for all units.
- */
+static void initialize_security_policies(void) +{
- /* Put OCRAM in non-secure */
- writel(0x003f0000, &noc_fw_ocram_base->region0);
- writel(0x1, &noc_fw_ocram_base->enable);
- /* Put DDR in non-secure */
- writel(0xffff0000, &noc_fw_ddr_l3_base->hpsregion0addr);
- writel(0x1, &noc_fw_ddr_l3_base->enable);
+}
+int arch_early_init_r(void) +{
- initialize_security_policies();
- /* Configure the L2 controller to make SDRAM start at 0 */
- writel(0x1, &pl310->pl310_addr_filter_start);
- /* assert reset to all except L4WD0 and L4TIMER0 */
- reset_assert_all_peripherals_except_l4wd0_l4timer0();
- /* configuring the clock based on handoff */
- /* TODO: Add call to cm_basic_init() */
- /* Add device descriptor to FPGA device table */
- socfpga_fpga_add();
- return 0;
+}
+#else
+static struct nic301_registers *nic301_regs =
- (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
/*
- Convert all NIC-301 AMBA slaves from secure to non-secure
*/ @@ -430,3 +481,4 @@ U_BOOT_CMD( "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" "" ); +#endif