[PATCH V2 04/19] doc: board: ti: j721e: Update with boot flow diagram

27 Jul 2023

Update the bootflow svg diagram instead of the ascii version
Reviewed-by: Neha Malcom Francis n-francis@ti.com
Signed-off-by: Nishanth Menon nm@ti.com
---
Changes since V1
* Picked up reviewed by, boot dia updates
V1: https://lore.kernel.org/all/20230727080027.2817701-5-nm@ti.com/
doc/board/ti/img/boot_diagram_j721e.svg | 2012 +++++++++++++++++++++++
 doc/board/ti/j721e_evm.rst              |   91 +-
 2 files changed, 2013 insertions(+), 90 deletions(-)
 create mode 100644 doc/board/ti/img/boot_diagram_j721e.svg

diff --git a/doc/board/ti/img/boot_diagram_j721e.svg b/doc/board/ti/img/boot_diagram_j721e.svg
new file mode 100644
index 000000000000..e61af5b76708
--- /dev/null
+++ b/doc/board/ti/img/boot_diagram_j721e.svg
@@ -0,0 +1,2012 @@
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diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst
index 1cc32a242dde..2659c5ea0dd2 100644
--- a/doc/board/ti/j721e_evm.rst
+++ b/doc/board/ti/j721e_evm.rst
@@ -34,96 +34,7 @@ Boot Flow:
 Boot flow is similar to that of AM65x SoC and extending it with remoteproc
 support. Below is the pictorial representation of boot flow:
-.. code-block:: text - - +--------------- - |        DMSC - +--------------- - |    +--------+ - |    |  Reset | - |    +--------+ - |         : - |    +--------+ - |    | *ROM* - |    +--------+ - |    |        | - |    |  ROM   | - |    |services| - |    |        | - |    |        | - |    |        | - |    | - |    |        | - |    |        | - |    |        | - |    |        | - |    |        | - |    |        | - |    |        | - |    |        | - |    |        | - |    |        | - |    | Start  | - |    | - |    |Firmware| - |    +--------+ - |        : - |    +---------+ - |    | *SYSFW* | - |    +---------+ - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    |  TIFS   | - |    |Services | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    | - |    +---------+ - | - +--------------- +.. image:: img/boot_diagram_j721e.svg

---------------------------------------------------------+-----------------------+ |      MCU R5           |        A72            |  MAIN R5/C66x/C7x     | ---------------------------------------------------------+-----------------------+ |                       |                       |                       | |                       |                       |                       | |                       |                       |                       | |                       |                       |                       | |   +-----------+       |                       |                       | |----------|-->| Reset rls |       |                       |                       | |   +-----------+       |                       |                       | |         :             |                       |                       | |         :             |                       |                       | |         :             |                       |                       | |   +-------------+     |                       |                       | |   |  *R5 ROM*   |     |                       |                       | |   +-------------+     |                       |                       | |<---------|---|Load and auth|     |                       |                       | |   | tiboot3.bin |     |                       |                       | |   +-------------+     |                       |                       | |         :             |                       |                       | |         :             |                       |                       | |         :             |                       |                       | |   +-------------+     |                       |                       | |   |  *R5 SPL*   |     |                       |                       | |   +-------------+     |                       |                       | |   |    Load     |     |                       |                       | |   |  sysfw.itb  |     |                       |                       | |   +-------------+     |                       |                       | System |<---------|---|    Start    |     |                       |                       | |   |    SYSFW    |     |                       |                       | |   +-------------+     |                       |                       | |   |             |     |                       |                       | |   |   Load      |     |                       |                       | |   |   system    |     |                       |                       | |   | Config data |     |                       |                       | |<--------|---|             |     |                       |                       | |         |   +-------------+     |                       |                       | |         |   |    DDR      |     |                       |                       | |         |   |   config    |     |                       |                       | |         |   +-------------+     |                       |                       | |         |   |    Load     |     |                       |                       | |         |   |  tispl.bin  |     |                       |                       | |         |   +-------------+     |                       |                       | |         |   |   Load R5   |     |                       |                       | |         |   |   firmware  |     |                       |                       | |         |   +-------------+     |                       |                       | |<--------|---| Start A72   |     |                       |                       | |         |   | and jump to |     |                       |                       | |         |   | DM fw image |     |                       |                       | |         |   +-------------+     |                       |                       | |         |                       |     +-----------+     |                       | |---------|-----------------------|---->| Reset rls |     |                       | |         |                       |     +-----------+     |                       | |                       |          :            |                       | |                       |     +-------------+   |                       | |<--------|-----------------------|---->|*TF-A/OP-TEE*|   |                       | |         |                       |     +-------------+   |                       | |         |                       |          :            |                       | |         |                       |     +-----------+     |                       | |<--------|-----------------------|---->| *A72 SPL* |     |                       | |         |                       |     +-----------+     |                       | |         |                       |     |   Load    |     |                       | |         |                       |     | u-boot.img|     |                       | |         |                       |     +-----------+     |                       | |         |                       |          :            |                       | |         |                       |     +-----------+     |                       | |<--------|-----------------------|---->| *U-Boot*  |     |                       | |         |                       |     +-----------+     |                       | |         |                       |     |  prompt   |     |                       | |         |                       |     +-----------+     |                       | |         |                       |     |  Load R5  |     |                       | |         |                       |     |  Firmware |     |                       | |         |                       |     +-----------+     |                       | |<--------|-----------------------|-----|  Start R5 |     |      +-----------+    | |---------|-----------------------|-----+-----------+-----|----->| R5 starts |    | |         |                       |     |  Load C6  |     |      +-----------+    | |         |                       |     |  Firmware |     |                       | |         |                       |     +-----------+     |                       | |<--------|-----------------------|-----|  Start C6 |     |      +-----------+    | |---------|-----------------------|-----+-----------+-----|----->| C6 starts |    | |         |                       |     |  Load C7  |     |      +-----------+    | |         |                       |     |  Firmware |     |                       | |         |                       |     +-----------+     |                       | |<--------|-----------------------|-----|  Start C7 |     |      +-----------+    | |---------|-----------------------|-----+-----------+-----|----->| C7 starts |    | |                       |                       |      +-----------+    | |                       |                       |                       | ---------------------------------------------------------+-----------------------+
- Here DMSC acts as master and provides all the critical services. R5/A72
   requests DMSC to get these services done as shown in the above diagram.
-- 
2.40.0


    