This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start.
If this is not done, the Linux system ends up booted with the L2 cache disabled.
Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com --- arch/arm/cpu/armv7/sunxi/board.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 49c9448..86cf4c9 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -69,6 +69,18 @@ void s_init(void) "mcr p15, 0, r0, c1, c0, 1\n"); #endif
+#if defined(CONFIG_SPL_FEL) && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I)) + /* For ARM Cortex-A8 based hardware (sun4i and sun5i), the L2EN bit is + * set by the BROM code in the "normal" mode, but not in the "FEL" mode. + * Here we fix this inconsistency in the Auxiliary Ctl reg by also + * setting the missing L2EN bit. + */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #2\n" + "mcr p15, 0, r0, c1, c0, 1\n" : : : "r0"); +#endif + clock_init(); timer_init(); gpio_init();