26 Dec
2020
26 Dec
'20
4:54 p.m.
The current PHY rework does the following things:
- Configure 125MHz clock
- Setup the TX clock delay (RX is enabled by default),
- Setup reserved bits to avoid voltage peak
The clock delays are nowadays already configured by the PHY driver (in ar803x_delay_config). The code for that can simply be dropped. The clock speed can also be configured by the PHY driver by adding the device tree property "qca,clk-out-frequency". What is left is setting up the undocumented reserved bits to avoid the voltage peak problem. I slightly improved its documentation while updating the board's PHY rework code. Signed-off-by: Sebastian Reichel sebastian.reichel@collabora.com
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
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