Acked-by: Ruchika Guptaruchika.gupta@freescale.com
-----Original Message----- From: Sun York-R58495 Sent: Sunday, July 19, 2015 3:44 AM To: Gupta Ruchika-R66431 Subject: Re: [PATCH 2/3] crypto/fsl: fix snooping for write transactions
Ruchika,
Please comment/ack.
York
On 07/08/2015 07:24 AM, Horia Geantă wrote:
HW coherency won't work properly for CAAM write transactions if AWCACHE is left to default (POR) value - 4'b0001. It has to be programmed to 4'b0010.
For platforms that have HW coherency support: -PPC-based: the update has no effect; CAAM coherency already works due to the IOMMU (PAMU) driver setting the correct memory coherency attributes -ARM-based: the update fixes cache coherency issues, since IOMMU (SMMU) driver is not programmed to behave similar to PAMU
Fixes: b9eebfade974c ("fsl_sec: Add hardware accelerated SHA256 and SHA1") Signed-off-by: Horia Geantă horia.geanta@freescale.com Reviewed-by: Aneesh Bansal aneesh.bansal@freescale.com Reviewed-by: Mingkai Hu Mingkai.Hu@freescale.com
drivers/crypto/fsl/jr.c | 10 ++++++---- drivers/crypto/fsl/jr.h | 2 ++ 2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index f99d59480c81..e2bd913aa259 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -459,14 +459,16 @@ static int rng_init(void)
int sec_init(void) {
- int ret = 0;
-#ifdef CONFIG_PHYS_64BIT ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; uint32_t mcr = sec_in32(&sec->mcfgr);
- int ret = 0;
- sec_out32(&sec->mcfgr, mcr | 1 << MCFGR_PS_SHIFT);
- mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 <<
MCFGR_AWCACHE_SHIFT);
+#ifdef CONFIG_PHYS_64BIT
- mcr |= (1 << MCFGR_PS_SHIFT);
#endif
- sec_out32(&sec->mcfgr, mcr);
- ret = jr_init(); if (ret < 0) { printf("SEC initialization failed\n"); diff --git
a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index cce2c589ce0b..152606008845 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -21,6 +21,8 @@ #define MCFGR_SWRST ((uint32_t)(1)<<31) /* Software Reset */ #define MCFGR_DMA_RST ((uint32_t)(1)<<28) /* DMA Reset */ #define MCFGR_PS_SHIFT 16 +#define MCFGR_AWCACHE_SHIFT 8 +#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) #define JR_INTMASK 0x00000001 #define JRCR_RESET 0x01 #define JRINT_ERR_HALT_INPROGRESS 0x4