Hi
On Dec 4, 2015 5:50 PM, "Eric Nelson" eric@nelint.com wrote:
Hi all,
On 12/04/2015 09:08 AM, Eric Nelson wrote: ...
I think you're onto something.
According to the i.MX35 reference manual, which I think was the origin of this patch, the low four bits of the SYSCTL register of the SDHC5 3 - SDCLKEN 2 - PEREN 1 - HCKEN 0 - IPGEN
See page 603 of http://cache.freescale.com/files/dsp/doc/ref_manual/IMX35RM.pdf
But in the i.MX6 reference manual, the low four bits are reserved and say "Always write as 1".
See pages 5679-5680 of http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf
It appears that when this patch was ported from the Freescale version, the test for "is_usdhc" was lost.
http://git.denx.de/?p=u-boot.git;a=commitdiff;h=7a5b80297bc6cef0c10e5f57ac04...
Happy if you fix down your problem
Michael
Following up, this code is bugged on i.MX6:
http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/mmc/fsl_esdhc.c;h=c5054d66...
As are a couple of other things in the driver, as seen by trying to compile without the constants for the low 4 bits:
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index aa1b4cf..a4b87ce 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -25,10 +25,12 @@ #define SYSCTL_INITA 0x08000000 #define SYSCTL_TIMEOUT_MASK 0x000f0000 #define SYSCTL_CLOCK_MASK 0x0000fff0 +#if !defined(CONFIG_MX6) #define SYSCTL_CKEN 0x00000008 #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 +#endif #define SYSCTL_RSTA 0x01000000 #define SYSCTL_RSTC 0x02000000 #define SYSCTL_RSTD 0x04000000