Implement early TPS6586X PMIC rail configuration setting SM0 being VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
While those are PMIC power-up defaults the SoC might have been reset separately with certain rails being left at lower DVFS states which is e.g. the case upon watchdog reset while otherwise nearly idling.
This fixes an issue of the Colibri T20 being stuck in U-Boot's SPL upon watchdog reset (e.g. running downstream L4T Linux kernel as there exists no mainline Tegra20 watchdog driver as of yet).
The last patch in this series is not really related but just gets rid of a spurious MAX_I2C_RETRY define in the Colibri T20's board file.
Marcel Ziswiler (3): arm: tegra20: implement early pmic rail configuration colibri_t20: enable early pmic rail configuration colibri_t20: get rid of spurious MAX_I2C_RETRY define
arch/arm/mach-tegra/tegra20/cpu.c | 76 ++++++++++++++++++++++++++++++++- board/toradex/colibri_t20/colibri_t20.c | 1 - include/configs/colibri_t20.h | 2 + 3 files changed, 77 insertions(+), 2 deletions(-)