The dram initialization sequence should be in order. This patch add mb for the dram intialization code to make sure the compiler do not disorder the code.
Signed-off-by: Jason Jin Jason.jin@freescale.com --- arch/m68k/include/asm/io.h | 2 ++ board/freescale/m5253demo/m5253demo.c | 4 ++++ 2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h index 531f420..d86eaf9 100644 --- a/arch/m68k/include/asm/io.h +++ b/arch/m68k/include/asm/io.h @@ -81,6 +81,8 @@ #define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) #endif
+#define mb() __asm__ __volatile__ ("" : : : "memory") + extern inline void _insb(volatile u8 * port, void *buf, int ns) { u8 *data = (u8 *) buf; diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 4772074..8ffb2cc 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -27,6 +27,7 @@ #include <common.h> #include <asm/immap.h> #include <netdev.h> +#include <asm/io.h>
int checkboard(void) { @@ -63,10 +64,12 @@ phys_size_t initdram(int board_type) __asm__("nop");
mbar_writeLong(MCFSIM_DACR0, 0x0000322c); + mb(); __asm__("nop");
/* Write to this block to initiate precharge */ *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; + mb(); __asm__("nop");
/* Set RE bit in DACR */ @@ -83,6 +86,7 @@ phys_size_t initdram(int board_type) __asm__("nop");
*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; + mb(); }
return dramsize;