On 08/13/2015 11:54 PM, Yuan Yao wrote:
Affects: DDR Description: Memory controller performance is not optimal with default internal target queue register values. Impact: Memory controller performance is not optimal. Workaround: Write a value of 63b2_0002h to address: 157_020Ch.
Signed-off-by: Yuan Yao yao.yuan@freescale.com
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- board/freescale/ls1021aqds/ls1021aqds.c | 10 ++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 10 ++++++++++ 3 files changed, 21 insertions(+), 1 deletion(-)
Yuan,
This is a wrong place to implement this workaround. It is a SoC erratum, not a board erratum. This erratum applies to both LS1021A and LS2085A. The workaround for LS2085A is already implemented in drivers/ddr/fsl/fsl_ddr_gen4.c. LS1021A supports both DDR3 and DDR4 modes. I started a discussion (CC'ed you) with the designer to clarify if both modes are impacted. If yes, you can add the workaround in drivers/ddr/fsl/arm_ddr_gen3.c, and make sure to add proper address offset in drivers/ddr/fsl/fsl_ddr_gen4.c.
York