12 Mar
2014
12 Mar
'14
9:04 p.m.
On Sun, Mar 09, 2014 at 03:56:52PM +0200, Vasili Galka wrote:
The logic determining SPI "write" transfer completion was faulty. At certain conditions (e.g. slow SPI clock freq) the transfers were interrupted before completion. Both EOT and TXS flags of channel status registeer shall be checked to ensure that all data was transferred. Tested on AM3359 chip.
Signed-off-by: Vasili Galka vasili@visionmap.com
Applied to u-boot-ti/master, thanks!
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Tom