
15 Mar
2006
15 Mar
'06
11:01 p.m.
On Mar 15, 2006, at 4:38 PM, Ben Warren wrote:
I'm not sure about the 8xx PowerQUICCs, but other Freescale CPUs with multiple ethernet ports support MII data plane on all ports but only have one MDIO port (control plane for MII). Maybe that's why the code is this way?
That's exactly why.
-- Dan