Hello Sekhar,
I am working on reducing boot time on an L138 EVM and SPI flash transfer speed is currently the worst offender. U-Boot transfers from the SPI flash at 0.6Mbytes/s, this a lot slower than I would expect for a 50MHz SPI clock. Using a scope we found that the chip select is active throughout the transfer (as expected), we see ~160ns bursts of activity on the clock line for each byte transferred (8 bits @ 50MHz) with 1us idle periods in between. Where does the 1us delay between byte transfers come from? Is reading data bytes from the SPI registers very slow or is writing to RAM one byte at a time slowing the transfer?
Reading the source I can see that FAST_READ is being issued to the SPI flash and, unless I am missing something, there shouldn't be a delay between byte transfers. Looking at the spi_xfer() function in drivers/spi/davinci_spi.c and the L138 SPI module documentation I can think of making the following improvements: call spi_readl(ds, BUF) only once per byte transfer; take advantage of the tx/rx buffers for pipelining; write received data to RAM 32bit at a time, instead of 1 byte at a time. Does any one of these improvements go in the right direction?
Thank you -- Delio