Re: [PATCH v1 2/3] arm: dts: rockchip: update cpu and gpu nodes

On 2022/7/30 07:49, Johan Jonker wrote:

In order to better compare the Linux rk3288.dtsi version with the u-boot version update the cpu and gpu nodes.

Changed: use operating-points-v2 update thermal for all cpus add labels to all cpus change gpu compatible change gpu interrupt names

Signed-off-by: Johan Jonker jbx6244@gmail.com

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

arch/arm/dts/rk3288.dtsi | 148 +++++++++++++++++++++++++++++---------- 1 file changed, 111 insertions(+), 37 deletions(-)

diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index c46741b0..6b03a63c 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -45,44 +45,99 @@ device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x500>;

• 	operating-points = <
  

• 		/* KHz    uV */
  

• 		1800000 1400000
  

• 		1704000 1350000
  

• 		1608000 1300000
  

• 		1512000 1250000
  

• 		1416000 1200000
  

• 		1200000 1100000
  

• 		1008000 1050000
  

• 		 816000 1000000
  

• 		 696000  950000
  

• 		 600000  900000
  

• 		 408000  900000
  

• 		 216000  900000
  

• 		 126000  900000
  

• 	>;
  

• 	resets = <&cru SRST_CORE0>;
  

• 	operating-points-v2 = <&cpu_opp_table>;
  #cooling-cells = <2>; /* min followed by max */
  clock-latency = <40000>;
  clocks = <&cru ARMCLK>;
  

• 	resets = <&cru SRST_CORE0>;
  

• 	dynamic-power-coefficient = <370>;
  

  };

• cpu@501 {
  

• cpu1: cpu@501 {
  device_type = "cpu";
  compatible = "arm,cortex-a12";
  reg = <0x501>;
  resets = <&cru SRST_CORE1>;
  

• 	operating-points-v2 = <&cpu_opp_table>;
  

• 	#cooling-cells = <2>; /* min followed by max */
  

• 	clock-latency = <40000>;
  

• 	clocks = <&cru ARMCLK>;
  

• 	dynamic-power-coefficient = <370>;
  

  };

• cpu@502 {
  

• cpu2: cpu@502 {
  device_type = "cpu";
  compatible = "arm,cortex-a12";
  reg = <0x502>;
  resets = <&cru SRST_CORE2>;
  

• 	operating-points-v2 = <&cpu_opp_table>;
  

• 	#cooling-cells = <2>; /* min followed by max */
  

• 	clock-latency = <40000>;
  

• 	clocks = <&cru ARMCLK>;
  

• 	dynamic-power-coefficient = <370>;
  

  };

• cpu@503 {
  

• cpu3: cpu@503 {
  device_type = "cpu";
  compatible = "arm,cortex-a12";
  reg = <0x503>;
  resets = <&cru SRST_CORE3>;
  

• 	operating-points-v2 = <&cpu_opp_table>;
  

• 	#cooling-cells = <2>; /* min followed by max */
  

• 	clock-latency = <40000>;
  

• 	clocks = <&cru ARMCLK>;
  

• 	dynamic-power-coefficient = <370>;
  

• };
  

• };
• cpu_opp_table: opp-table-0 {

• compatible = "operating-points-v2";
  

• opp-shared;
  

• opp-126000000 {
  

• 	opp-hz = /bits/ 64 <126000000>;
  

• 	opp-microvolt = <900000>;
  

• };
  

• opp-216000000 {
  

• 	opp-hz = /bits/ 64 <216000000>;
  

• 	opp-microvolt = <900000>;
  

• };
  

• opp-312000000 {
  

• 	opp-hz = /bits/ 64 <312000000>;
  

• 	opp-microvolt = <900000>;
  

• };
  

• opp-408000000 {
  

• 	opp-hz = /bits/ 64 <408000000>;
  

• 	opp-microvolt = <900000>;
  

• };
  

• opp-600000000 {
  

• 	opp-hz = /bits/ 64 <600000000>;
  

• 	opp-microvolt = <900000>;
  

• };
  

• opp-696000000 {
  

• 	opp-hz = /bits/ 64 <696000000>;
  

• 	opp-microvolt = <950000>;
  

• };
  

• opp-816000000 {
  

• 	opp-hz = /bits/ 64 <816000000>;
  

• 	opp-microvolt = <1000000>;
  

• };
  

• opp-1008000000 {
  

• 	opp-hz = /bits/ 64 <1008000000>;
  

• 	opp-microvolt = <1050000>;
  

• };
  

• opp-1200000000 {
  

• 	opp-hz = /bits/ 64 <1200000000>;
  

• 	opp-microvolt = <1100000>;
  

• };
  

• opp-1416000000 {
  

• 	opp-hz = /bits/ 64 <1416000000>;
  

• 	opp-microvolt = <1200000>;
  

• };
  

• opp-1512000000 {
  

• 	opp-hz = /bits/ 64 <1512000000>;
  

• 	opp-microvolt = <1300000>;
  

• };
  

• opp-1608000000 {
  

• 	opp-hz = /bits/ 64 <1608000000>;
  

• 	opp-microvolt = <1350000>;
  

  }; };

@@ -374,12 +429,18 @@ map0 { trip = <&cpu_alert0>; cooling-device =

• 				<&cpu0 THERMAL_NO_LIMIT 6>;
  

• 				<&cpu0 THERMAL_NO_LIMIT 6>,
  

• 				<&cpu1 THERMAL_NO_LIMIT 6>,
  

• 				<&cpu2 THERMAL_NO_LIMIT 6>,
  

• 				<&cpu3 THERMAL_NO_LIMIT 6>;
  	};
  	map1 {
  		trip = <&cpu_alert1>;
  		cooling-device =
  

• 				<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  

• 				<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  

• 				<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  

• 				<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  

• 				<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  	};
  };
  

  };

@@ -900,31 +961,44 @@ };

gpu: gpu@ffa30000 {

• compatible = "arm,malit764",
  

• 	     "arm,malit76x",
  

• 	     "arm,malit7xx",
  

• 	     "arm,mali-midgard";
  

• compatible = "rockchip,rk3288-mali", "arm,mali-t760";
  

  reg = <0xffa30000 0x10000>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

• interrupt-names = "JOB", "MMU", "GPU";
  

• interrupt-names = "job", "mmu", "gpu";
  

  clocks = <&cru ACLK_GPU>;

• clock-names = "aclk_gpu";
  

• operating-points = <
  

• 	/* KHz uV */
  

• 	100000 950000
  

• 	200000 950000
  

• 	300000 1000000
  

• 	400000 1100000
  

• 	/* 500000 1200000 - See crosbug.com/p/33857 */
  

• 	600000 1250000
  

• >;
  

• operating-points-v2 = <&gpu_opp_table>;
  

  #cooling-cells = <2>; /* min followed by max */ power-domains = <&power RK3288_PD_GPU>; status = "disabled"; };

• gpu_opp_table: opp-table-1 {

• compatible = "operating-points-v2";
  

• opp-100000000 {
  

• 	opp-hz = /bits/ 64 <100000000>;
  

• 	opp-microvolt = <950000>;
  

• };
  

• opp-200000000 {
  

• 	opp-hz = /bits/ 64 <200000000>;
  

• 	opp-microvolt = <950000>;
  

• };
  

• opp-300000000 {
  

• 	opp-hz = /bits/ 64 <300000000>;
  

• 	opp-microvolt = <1000000>;
  

• };
  

• opp-400000000 {
  

• 	opp-hz = /bits/ 64 <400000000>;
  

• 	opp-microvolt = <1100000>;
  

• };
  

• opp-600000000 {
  

• 	opp-hz = /bits/ 64 <600000000>;
  

• 	opp-microvolt = <1250000>;
  

• };
  

• };

• dmac_bus_s: dma-controller@ffb20000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xffb20000 0x4000>;