From: Teik Heng Chong teik.heng.chong@intel.com
Clean up bit-shift by zero bit
Signed-off-by: Teik Heng Chong teik.heng.chong@intel.com Signed-off-by: Tingting Meng tingting.meng@intel.com --- drivers/ddr/altera/sdram_soc64.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 02019ac9e5..add7df01a5 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -92,7 +92,7 @@ struct altera_sdram_plat { #define NIOSRESERVED2 0x118
#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ - (((x) >> 0) & 0x1F) + ((x) & 0x1F) #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \ (((x) >> 5) & 0x1F) #define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \ @@ -103,7 +103,7 @@ struct altera_sdram_plat { (((x) >> 16) & 0x7)
#define CTRLCFG0_CFG_MEMTYPE(x) \ - (((x) >> 0) & 0xF) + ((x) & 0xF) #define CTRLCFG0_CFG_DIMM_TYPE(x) \ (((x) >> 4) & 0x7) #define CTRLCFG0_CFG_AC_POS(x) \ @@ -112,17 +112,17 @@ struct altera_sdram_plat { (((x) >> 9) & 0x1F)
#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \ - (((x) >> 0) & 0x1F) + ((x) & 0x1F) #define CTRLCFG1_CFG_ADDR_ORDER(x) \ (((x) >> 5) & 0x3) #define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ (((x) >> 7) & 0x1)
#define DRAMTIMING0_CFG_TCL(x) \ - (((x) >> 0) & 0x7F) + ((x) & 0x7F)
#define CALTIMING0_CFG_ACT_TO_RDWR(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING0_CFG_ACT_TO_PCH(x) \ (((x) >> 6) & 0x3F) #define CALTIMING0_CFG_ACT_TO_ACT(x) \ @@ -131,7 +131,7 @@ struct altera_sdram_plat { (((x) >> 18) & 0x3F)
#define CALTIMING1_CFG_RD_TO_RD(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING1_CFG_RD_TO_RD_DC(x) \ (((x) >> 6) & 0x3F) #define CALTIMING1_CFG_RD_TO_RD_DB(x) \ @@ -142,7 +142,7 @@ struct altera_sdram_plat { (((x) >> 24) & 0x3F)
#define CALTIMING2_CFG_RD_TO_WR_DB(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING2_CFG_RD_TO_WR_PCH(x) \ (((x) >> 6) & 0x3F) #define CALTIMING2_CFG_RD_AP_TO_VALID(x) \ @@ -153,7 +153,7 @@ struct altera_sdram_plat { (((x) >> 24) & 0x3F)
#define CALTIMING3_CFG_WR_TO_WR_DB(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING3_CFG_WR_TO_RD(x) \ (((x) >> 6) & 0x3F) #define CALTIMING3_CFG_WR_TO_RD_DC(x) \ @@ -164,7 +164,7 @@ struct altera_sdram_plat { (((x) >> 24) & 0x3F)
#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING4_CFG_PCH_TO_VALID(x) \ (((x) >> 6) & 0x3F) #define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \ @@ -175,7 +175,7 @@ struct altera_sdram_plat { (((x) >> 26) & 0x3F)
#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ - (((x) >> 0) & 0xFF) + ((x) & 0xFF)
/* Firewall DDR scheduler MPFE */ #define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004