Hi FUKAUMI,
Thanks for the review comments, I will correct this in the next revision.
@marek.vasut+renesas@mailbox.org marek.vasut+renesas@mailbox.org, @festevam@denx.de festevam@denx.de, @Simon Glass sjg@chromium.org , @Kever Yang kever.yang@rock-chips.com, @Philipp Tomsich philipp.tomsich@vrull.eu Any comments from your side?
Best Regards, Akash
On Tue, Feb 7, 2023 at 8:32 AM FUKAUMI Naoki naoki@radxa.com wrote:
sorry, few more corrections...
On 2/7/23 10:07, FUKAUMI Naoki wrote:
hi
thank you very much for your work!
On 2/7/23 02:56, Akash Gajjar wrote:
Add Radxa Rock Pi 3A support.
"ROCK 3 Model A" or "ROCK 3A". uppercase "ROCK", no "Pi" please.
sync rk3568-rock-3a.dts from Linux 6.2.0-rc7
it seems several parts of dts are omitted. why?
Board Specification
- Rockchip RK3568
- 2/4/8 GB Dual-Channel LPDDR4
no "Dual-Channel"
- eMMC socket,SD card slot
- GbE LAN
- PCIe 3.0/2.0
- M.2 Connector
- HDMI In/Out, DP, MIPI DSI/CSI
no "HDMI In".
no "DP"
-- FUKAUMI Naoki
- USB 3.0, 2.0
- 40-pin GPIO expansion ports
- DC 12V/2A
Type-C PD 2.0 or QC 3.0/2.0, 9V/2A - 20V/2A.
Signed-off-by: Akash Gajjar gajjar04akash@gmail.com
arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 24 +++ arch/arm/dts/rk3568-rock-3a.dts | 214 ++++++++++++++++++++++++ configs/rock-pi-3a-rk3568_defconfig | 69 ++++++++ 4 files changed, 309 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-rock-3a.dts create mode 100644 configs/rock-pi-3a-rk3568_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d9b719f85d..7c28418c82 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -165,7 +165,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ROCKCHIP_RK3568) += \
- rk3568-evb.dtb
- rk3568-evb.dtb \
- rk3568-rock-3a.dtb dtb-$(CONFIG_ROCKCHIP_RV1108) += \ rv1108-elgin-r1.dtb \
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi new file mode 100644 index 0000000000..42c5b6a6c5 --- /dev/null +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- (C) Copyright 2021 Rockchip Electronics Co., Ltd
- (c) Copyright 2023 Akash Gajjar gajjar04akash@gmail.com
- */
+#include "rk356x-u-boot.dtsi"
+/ {
- chosen {
stdout-path = &uart2;u-boot,spl-boot-order = "same-as-spl", &sdmmc0;- };
+};
+&sdmmc0 {
- status = "okay";
+};
redundant?
Best regards,
-- FUKAUMI Naoki
+&uart2 {
- clock-frequency = <24000000>;
- u-boot,dm-spl;
- status = "okay";
+}; diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts new file mode 100644 index 0000000000..0ff511d6a2 --- /dev/null +++ b/arch/arm/dts/rk3568-rock-3a.dts @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- Copyright (c) 2023 Akash Gajjar gajjar04akash@gmail.com
- */
+/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3568.dtsi"
+/ {
- model = "Radxa ROCK3 Model A";
- compatible = "radxa,rock3a", "rockchip,rk3568";
- chosen: chosen {
stdout-path = "serial2:1500000n8";- };
- gmac1_clkin: external-gmac1-clock {
compatible = "fixed-clock";clock-frequency = <125000000>;clock-output-names = "gmac1_clkin";#clock-cells = <0>;- };
- vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";regulator-name = "vcc12v_dcin";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <12000000>;regulator-max-microvolt = <12000000>;- };
- vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";regulator-name = "vcc3v3_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc12v_dcin>;- };
- vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc12v_dcin>;- };
- vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_usb";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc12v_dcin>;- };
- vcc5v0_usb_host: vcc5v0-usb-host-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";regulator-name = "vcc5v0_usb_host";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc5v0_usb>;- };
- vcc5v0_usb_hub: vcc5v0-usb-hub-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";regulator-name = "vcc5v0_usb_hub";regulator-always-on;vin-supply = <&vcc5v0_usb>;- };
- vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";regulator-name = "vcc5v0_usb_otg";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc5v0_usb>;- };
- vcc_cam: vcc-cam-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";regulator-name = "vcc_cam";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc3v3_sys>;regulator-state-mem {regulator-off-in-suspend;};- };
- vcc_mipi: vcc-mipi-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";regulator-name = "vcc_mipi";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc3v3_sys>;regulator-state-mem {regulator-off-in-suspend;};- };
+};
+&gmac1 {
- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>,
<&gmac1_clkin>;
- clock_in_out = "input";
- phy-handle = <&rgmii_phy1>;
- phy-mode = "rgmii-id";
- pinctrl-names = "default";
- status = "okay";
+};
+&mdio1 {
- rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";reg = <0x0>;pinctrl-names = "default";reset-assert-us = <20000>;reset-deassert-us = <100000>;reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;- };
+};
+&sdmmc0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- sd-uhs-sdr104;
- status = "okay";
+};
+&uart2 {
- status = "okay";
+};
+&usb_host0_ehci {
- status = "okay";
+};
+&usb_host0_ohci {
- status = "okay";
+};
+&usb_host0_xhci {
- extcon = <&usb2phy0>;
- status = "okay";
+};
+&usb_host1_ehci {
- status = "okay";
+};
+&usb_host1_ohci {
- status = "okay";
+};
+&usb_host1_xhci {
- status = "okay";
+};
+&usb2phy0 {
- status = "okay";
+};
+&usb2phy0_host {
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
+};
+&usb2phy0_otg {
- phy-supply = <&vcc5v0_usb_otg>;
- status = "okay";
+};
+&usb2phy1 {
- status = "okay";
+};
+&usb2phy1_host {
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
+};
+&usb2phy1_otg {
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
+}; diff --git a/configs/rock-pi-3a-rk3568_defconfig b/configs/rock-pi-3a-rk3568_defconfig new file mode 100644 index 0000000000..40732910be --- /dev/null +++ b/configs/rock-pi-3a-rk3568_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_EVB_RK3568=y +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +# CONFIG_BINMAN_FDT is not set +CONFIG_ERRNO_STR=y