Hi Fabio
On Wed, Oct 26, 2022 at 2:18 AM Fabio Estevam festevam@denx.de wrote:
Hi Tim,
On 25/10/2022 20:23, Tim Harvey wrote:
Fabio,
This resolves the issue. Why would the kernel not suffer from this as well? We are essentially saying if the FIFO is not full but also not empty we need to wait.... so do we have a FIFO size of 1 or something here as opposed to the kernel?
The FIFO has a fixed size of 32 chars.
Kernel uses TXTL, which "controls the threshold at which a maskable interrupt is generated by the TxFIFO".
We do not use interrupts in U-Boot. Prior to Johannes' patch, we only checked for the TXFIFO empty condition, which avoided sending data when nothing was available inside the FIFO (under-run condition).
Johannes' patch handles over-run condition.
My patch guarantees that both over-run and under-run conditions are handled.
When the number of chars in the FIFO is 1, 2, 3,...30, the transmission can safely happen. Special cases are FIFO empty and FIFO full, which returns -EAGAIN to the serial core.
Can you explain it better? If FIFO is empty there are no chars in the serial, and the transmission can happen only when you have at least one byte in the fifo. The underrun condition in general is when the start of tx is enabled but you have no bytes to send at the time that bytes are needed. Was the case to limit the change on the architecture that was tested?
Michael
Regards,
Fabio Estevam
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