Update bootscript and its hdr addresses for Layerscape Chasis 3 based platforms instead of individual SoCs.
Signed-off-by: Sumit Garg sumit.garg@nxp.com Signed-off-by: Udit Agarwal udit.agarwal@nxp.com ---
Changes for V2: Modified the subject
arch/arm/include/asm/fsl_secure_boot.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 933e09c..f34ffc7 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -84,7 +84,7 @@ * Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD) */ -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) || \ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ defined(CONFIG_SD_BOOT) #define CONFIG_BOOTSCRIPT_COPY_RAM #endif @@ -92,11 +92,11 @@ * The address needs to be modified according to NOR, NAND, SD and * DDR memory map */ -#ifdef CONFIG_LS2080A -#define CONFIG_BS_HDR_ADDR_DEVICE 0x583920000 -#define CONFIG_BS_ADDR_DEVICE 0x583900000 -#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000 -#define CONFIG_BS_ADDR_RAM 0xa3900000 +#ifdef CONFIG_FSL_LSCH3 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000 +#define CONFIG_BS_ADDR_DEVICE 0x580e00000 +#define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000 +#define CONFIG_BS_ADDR_RAM 0xa0e00000 #define CONFIG_BS_HDR_SIZE 0x00002000 #define CONFIG_BS_SIZE 0x00001000 #else