
9 May
2008
9 May
'08
7:43 p.m.
In message 1210354701.2948.14.camel@r54964-12.am.freescale.net you wrote:
I don't think this patch is necessary because for all e500v2 core, setting RSTCR is the right way to reset the board.
Agreed,t hat's how it should wor. But it doesn't on the syscon3 board.
I think you should check board FPGA. I met the similar problem before. Since FPGA did not correctly route the HRESET_REQ signal, setting RSTCR did not cause reset. After hardware person fixed the FPGA code, it worked fine.
Ummm... This is on a custom design, the syscon3 board. There is no FPGA there...
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
God made the integers; all else is the work of Man. - Kronecker