On Fri, Mar 11, 2016 at 4:52 PM, Steve Rae srae@broadcom.com wrote:
From: Jiandong Zheng jdzheng@broadcom.com
Add support for the iproc NAND, and enable on Cygnus and NSP boards.
Signed-off-by: Jiandong Zheng jdzheng@broadcom.com Signed-off-by: Steve Rae srae@broadcom.com
There was a previous attempt to implement this "iproc NAND" (see: http://patchwork.ozlabs.org/patch/505399), however, due to the amount of changes required, it seemed better to implement the code in a series of steps. This is the first step, where the "iproc_nand.c" is essentially an empty file (with one function required to allow this commit to build successfully).
RFC only - more changes are coming for "drivers/mtd/nand/iproc_nand.c"
Changes in v2:
- convert some CONFIG_* to Kconfig
arch/arm/include/asm/arch-bcmcygnus/configs.h | 11 ++- arch/arm/include/asm/arch-bcmnsp/configs.h | 11 ++- board/broadcom/bcmcygnus/Kconfig | 5 ++ board/broadcom/bcmnsp/Kconfig | 5 ++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/iproc_nand.c | 19 +++++ drivers/mtd/nand/iproc_nand_cygnus.h | 111 +++++++++++++++++++++++++ drivers/mtd/nand/iproc_nand_ns_plus.h | 113 ++++++++++++++++++++++++++ 8 files changed, 272 insertions(+), 4 deletions(-) create mode 100644 drivers/mtd/nand/iproc_nand.c create mode 100644 drivers/mtd/nand/iproc_nand_cygnus.h create mode 100644 drivers/mtd/nand/iproc_nand_ns_plus.h
diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index 3c07160..accf0a1 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -9,8 +9,6 @@
#include <asm/iproc-common/configs.h>
-/* uArchitecture specifics */
/* Serial Info */ /* Post pad 3 bytes after each reg addr */ #define CONFIG_SYS_NS16550_REG_SIZE (-4) @@ -33,4 +31,13 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_MII
+/* NAND configuration */ +#define CONFIG_CMD_NAND +#define CONFIG_NAND_IPROC +#define CONFIG_SYS_NAND_IPROC_TIMING_MODE 5 +#define CONFIG_SYS_NAND_BASE 0 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_MAX_NAND_CHIPS 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION
convert these 7 items to Kconfig [see: v3]
#endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h index 786deae..e547d4a 100644 --- a/arch/arm/include/asm/arch-bcmnsp/configs.h +++ b/arch/arm/include/asm/arch-bcmnsp/configs.h @@ -9,8 +9,6 @@
#include <asm/iproc-common/configs.h>
-/* uArchitecture specifics */
/* Serial Info */ /* no padding */ #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -19,4 +17,13 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_COM1 0x18000300
+/* NAND configuration */ +#define CONFIG_CMD_NAND +#define CONFIG_NAND_IPROC +#define CONFIG_SYS_NAND_IPROC_TIMING_MODE 5 +#define CONFIG_SYS_NAND_BASE 0 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_MAX_NAND_CHIPS 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION
convert these 7 items to Kconfig [see: v3]
#endif /* __ARCH_CONFIGS_H */ diff --git a/board/broadcom/bcmcygnus/Kconfig b/board/broadcom/bcmcygnus/Kconfig index faba4cf..4c5011f 100644 --- a/board/broadcom/bcmcygnus/Kconfig +++ b/board/broadcom/bcmcygnus/Kconfig @@ -12,4 +12,9 @@ config SYS_SOC config SYS_CONFIG_NAME default "bcm_ep_board"
+config SYS_BCM_CYGNUS
booldefault yselect SYS_NAND_SELF_INITendif diff --git a/board/broadcom/bcmnsp/Kconfig b/board/broadcom/bcmnsp/Kconfig index a975082..f55c4f9 100644 --- a/board/broadcom/bcmnsp/Kconfig +++ b/board/broadcom/bcmnsp/Kconfig @@ -12,4 +12,9 @@ config SYS_SOC config SYS_CONFIG_NAME default "bcm_ep_board"
+config SYS_BCM_NSPLUS
booldefault yselect SYS_NAND_SELF_INITendif diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 6fb3718..bb3adbc 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o +obj-$(CONFIG_NAND_IPROC) += iproc_nand.o obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o diff --git a/drivers/mtd/nand/iproc_nand.c b/drivers/mtd/nand/iproc_nand.c new file mode 100644 index 0000000..691b8d8 --- /dev/null +++ b/drivers/mtd/nand/iproc_nand.c @@ -0,0 +1,19 @@ +/*
- Copyright 2015 Broadcom Corporation.
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h>
+#if defined(CONFIG_SYS_BCM_CYGNUS) +#include "iproc_nand_cygnus.h" +#elif defined(CONFIG_SYS_BCM_NSPLUS) +#include "iproc_nand_ns_plus.h" +#else +#error "Unsupported configuration" +#endif
+void board_nand_init(void) +{ +} diff --git a/drivers/mtd/nand/iproc_nand_cygnus.h b/drivers/mtd/nand/iproc_nand_cygnus.h new file mode 100644 index 0000000..26a00a9 --- /dev/null +++ b/drivers/mtd/nand/iproc_nand_cygnus.h @@ -0,0 +1,111 @@ +/*
- Copyright 2015 Broadcom Corporation.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _IPROC_NAND_CYGNUS_H_ +#define _IPROC_NAND_CYGNUS_H_
+/*
- SoC specific definitions (Cygnus)
- */
+#define REG_NAND_BASE 0x18046000 +#define REG_NAND_IDM_BASE 0xf8105000
+#define NAND_STRAP_TYPE_MASK 0x000f0000 +#define NAND_STRAP_TYPE_SHIFT 16 +#define NAND_STRAP_PAGE_MASK 0x00300000 +#define NAND_STRAP_PAGE_SHIFT 20 +#define NAND_STRAP_WIDTH_MASK 0x01000000 +#define NAND_STRAP_WIDTH_SHIFT 24
+#define NAND_STRAP_TYPE_DATA \ +/* sector_1k, ecclevel, spare_size */ \ +{ \
{ 0, 0, 16 }, \{ 0, 1, 16 }, \{ 0, 4, 16 }, \{ 0, 8, 16 }, \{ 0, 8, 27 }, \{ 0, 12, 27 }, \{ 1, 12, 27 }, \{ 1, 15, 27 }, \{ 1, 20, 45 } \+}
+#define NAND_STRAP_PAGE_DATA \ +{ \
1024, 2048, 4096, 8192 \+}
+/*
- iProc NAND timing configurations for ONFI timing modes [0-5]
- Clock tick = 10ns
- Multiplier:
- x1: tWP tWH tRP tREH tCLH tALH
- x2: tCS tADL tWB tWHR
- */
+#define NAND_TIMING_DATA \ +{ \
/* ONFI timing mode 0 : */ \/* tWC=100ns tWP=50ns tWH=30ns */ \/* tRC=100ns tRP=50ns tREH=30ns */ \/* tCS=70ns tCLH=20ns tALH=20ns tADL=200ns */ \/* tWB=200ns tWHR=120ns tREA=40ns */ \{ \.timing1 = 0x6565435b, \.timing2 = 0x00001e85, \}, \/* ONFI timing mode 1 : */ \/* tWC=45 tWP=25ns tWH=15ns */ \/* tRC=50 tRP=25ns tREH=15ns */ \/* tCS=35ns tCLH=10ns tALH=10ns tADL=100ns */ \/* tWB=100ns tWHR=80ns tREA=30ns */ \{ \.timing1 = 0x33333236, \.timing2 = 0x00001064, \}, \/* ONFI timing mode 2 : */ \/* tWC=35ns tWP=17ns tWH=15ns */ \/* tRC=35ns tRP=17ns tREH=15ns */ \/* tCS=25ns tCLH=10ns tALH=10ns tADL=100ns */ \/* tWB=100ns tWHR=80ns tREA=25ns */ \{ \.timing1 = 0x32322226, \.timing2 = 0x00001063, \}, \/* ONFI timing mode 3 : */ \/* tWC=30ns tWP=15ns tWH=10ns */ \/* tRC=30ns tRP=15ns tREH=10ns */ \/* tCS=25ns tCLH=5ns tALH=5ns tADL=100ns */ \/* tWB=100ns tWHR=60ns tREA=20ns */ \{ \.timing1 = 0x22222126, \.timing2 = 0x00001043, \}, \/* ONFI timing mode 4 : */ \/* tWC=25ns tWP=12ns tWH=10ns */ \/* tRC=25ns tRP=12ns tREH=10ns */ \/* tCS=20ns tCLH=5ns tALH=5ns tADL=70ns */ \/* tWB=100ns tWHR=60ns tREA=20ns */ \{ \.timing1 = 0x21212114, \.timing2 = 0x00001042, \}, \/* ONFI timing mode 5 : */ \/* tWC=20ns tWP=10ns tWH=7ns */ \/* tRC=20ns tRP=10ns tREH=7ns */ \/* tCS=15ns tCLH=5ns tALH=5ns tADL=70ns */ \/* tWB=100ns tWHR=60ns tREA=16ns */ \{ \.timing1 = 0x11111114, \.timing2 = 0x00001042, \}, \+}
+#define NAND_MAX_CS 2
+#endif /* _IPROC_NAND_CYGNUS_H_ */ diff --git a/drivers/mtd/nand/iproc_nand_ns_plus.h b/drivers/mtd/nand/iproc_nand_ns_plus.h new file mode 100644 index 0000000..41d5da7 --- /dev/null +++ b/drivers/mtd/nand/iproc_nand_ns_plus.h @@ -0,0 +1,113 @@ +/*
- Copyright 2015 Broadcom Corporation.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _IPROC_NAND_NS_PLUS_H_ +#define _IPROC_NAND_NS_PLUS_H_
+/*
- SoC specific definitions (NorthStar Plus)
- */
+#define REG_NAND_BASE 0x18026000 +#define REG_NAND_IDM_BASE 0x1811b000 +#define REG_NAND_STRAPS_BASE 0x1803f2a0
+#define NAND_STRAP_TYPE_MASK 0x0000f000 +#define NAND_STRAP_TYPE_SHIFT 12 +#define NAND_STRAP_PAGE_MASK 0x00000c00 +#define NAND_STRAP_PAGE_SHIFT 10 +/* No bus width strap */ +#define NAND_STRAP_WIDTH_MASK 0x0 +#define NAND_STRAP_WIDTH_SHIFT 0
+#define NAND_STRAP_TYPE_DATA \ +/* sector_1k, ecclevel, spare_size */ \ +{ \
{ 0, 0, 16 }, \{ 0, 15, 16 }, /* Hamming ECC */ \{ 0, 4, 16 }, \{ 0, 8, 16 }, \{ 0, 8, 27 }, \{ 0, 12, 27 }, \{ 1, 12, 27 }, \{ 1, 15, 27 }, \{ 1, 20, 45 } \+}
+#define NAND_STRAP_PAGE_DATA \ +{ \
2048, 2048, 4096, 8192 \+}
+/*
- iProc NAND timing configurations for ONFI timing modes [0-5]
- Clock tick = 4ns
- Multiplier:
- x1: tWP tWH tRP tREH tCLH tALH
- x4: tCS tADL tWB tWHR
- */
+#define NAND_TIMING_DATA \ +{ \
/* ONFI timing mode 0 : */ \/* tWC=100ns tWP=50ns tWH=30ns */ \/* tRC=100ns tRP=50ns tREH=30ns */ \/* tCS=70ns tCLH=20ns tALH=20ns tADL=200ns */ \/* tWB=200ns tWHR=120ns tREA=40ns */ \{ \.timing1 = 0xfafa558d, \.timing2 = 0x00001a85, \}, \/* ONFI timing mode 1 : */ \/* tWC=45 tWP=25ns tWH=15ns */ \/* tRC=50 tRP=25ns tREH=15ns */ \/* tCS=35ns tCLH=10ns tALH=10ns tADL=100ns */ \/* tWB=100ns tWHR=80ns tREA=30ns */ \{ \.timing1 = 0x85853347, \.timing2 = 0x00000e64, \}, \/* ONFI timing mode 2 : */ \/* tWC=35ns tWP=17ns tWH=15ns */ \/* tRC=35ns tRP=17ns tREH=15ns */ \/* tCS=25ns tCLH=10ns tALH=10ns tADL=100ns */ \/* tWB=100ns tWHR=80ns tREA=25ns */ \{ \.timing1 = 0x54542347, \.timing2 = 0x00000e63, \}, \/* ONFI timing mode 3 : */ \/* tWC=30ns tWP=15ns tWH=10ns */ \/* tRC=30ns tRP=15ns tREH=10ns */ \/* tCS=25ns tCLH=5ns tALH=5ns tADL=100ns */ \/* tWB=100ns tWHR=60ns tREA=20ns */ \{ \.timing1 = 0x44442237, \.timing2 = 0x00000e43, \}, \/* ONFI timing mode 4 : */ \/* tWC=25ns tWP=12ns tWH=10ns */ \/* tRC=25ns tRP=12ns tREH=10ns */ \/* tCS=20ns tCLH=5ns tALH=5ns tADL=70ns */ \/* tWB=100ns tWHR=60ns tREA=20ns */ \{ \.timing1 = 0x43432235, \.timing2 = 0x00000e42, \}, \/* ONFI timing mode 5 : */ \/* tWC=20ns tWP=10ns tWH=7ns */ \/* tRC=20ns tRP=10ns tREH=7ns */ \/* tCS=15ns tCLH=5ns tALH=5ns tADL=70ns */ \/* tWB=100ns tWHR=60ns tREA=16ns */ \{ \.timing1 = 0x32321225, \.timing2 = 0x00000e42, \}, \+}
+#define NAND_MAX_CS 1
+#endif /* _IPROC_NAND_NS_PLUS_H_ */
1.8.5