This patch adds a brief introduction to the RISC-V architecture and the typical boot process used on a variety of RISC-V platforms.
Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com Reviewed-by: Samuel Holland samuel@sholland.org Reviewed-by: Simon Glass sjg@chromium.org --- Changes v1 -> v2 - Use 'boot phases' rather than 'boot stages' - Pick up Samuel and Simon's RB tags --- doc/arch/index.rst | 1 + doc/arch/riscv.rst | 43 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 doc/arch/riscv.rst
diff --git a/doc/arch/index.rst b/doc/arch/index.rst index b3e85f9bf3..b8da4b8c8e 100644 --- a/doc/arch/index.rst +++ b/doc/arch/index.rst @@ -11,6 +11,7 @@ Architecture-specific doc m68k mips nios2 + riscv sandbox/index sh x86 diff --git a/doc/arch/riscv.rst b/doc/arch/riscv.rst new file mode 100644 index 0000000000..6327dad8fb --- /dev/null +++ b/doc/arch/riscv.rst @@ -0,0 +1,43 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2023, Yu Chien Peter Lin peterlin@andestech.com + +RISC-V +====== + +Overview +-------- + +This document outlines the U-Boot boot process for the RISC-V architecture. +RISC-V is an open-source instruction set architecture (ISA) based on the +principles of reduced instruction set computing (RISC). It has been designed +to be flexible and customizable, allowing it to be adapted to different use +cases, from embedded systems to high performance servers. + +Typical Boot Process +-------------------- + +RISC-V production boot images typically include a U-Boot SPL for platform-specific +initialization. The U-Boot SPL then loads a FIT image (u-boot.itb), which contains +an SBI (Supervisor Binary Interface) firmware such as `OpenSBI https://github.com/riscv-software-src/opensbi`_, as well as a regular +U-Boot (or U-Boot proper) running in S-mode. Finally, the S-mode Operating System +is loaded. + +In between the boot phases, the hartid is passed through the a0 register, and the +start address of the devicetree is passed through the a1 register. + +The following diagram illustrates the boot process:: + + <----------( M-mode )--------><-------( S-mode )------> + +------------+ +---------+ +--------+ +--------+ + | U-Boot SPL |-->| SBI |--->| U-Boot |-->| OS | + +------------+ +---------+ +--------+ +--------+ + +To examine the boot process with the QEMU virt machine, you can follow the steps +in the following document: +:doc:`../board/emulation/qemu-riscv.rst` + +Toolchain +--------- + +You can build the `RISC-V GNU toolchain https://github.com/riscv-collab/riscv-gnu-toolchain`_ from scratch, or download a +pre-built toolchain from the `releases page https://github.com/riscv-collab/riscv-gnu-toolchain/releases`_.