On 9/26/07, robert lazarski robertlazarski@gmail.com wrote:
On 9/26/07, Jerry Van Baren gerald.vanbaren@smiths-aerospace.com wrote:
robert lazarski wrote:
.long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
You might not need this entry. I think you're covering it with the Flash mapping. This is probably true for some other boards, and I don't think it's your problem, but having two mappings for the same virtual address space is technically a programming error. It just happens that there's no negative side effect on e500.
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, * and must not collide with other TLB0 entries. */ .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,1,0,1,0,1)
What did you set CFG_INIT_RAM_ADDR to?
/* * TLB 0, 1: 128M Non-cacheable, guarded * 0xf8000000 128M FLASH * Out of reset this entry is only 4K. */ .long TLB1_MAS0(1, 1, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(1, 0, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,0,1,0,1,0,1)
Try reordering these entries so that TLB1, entry 0 is initialized before TLB1, entry 1. I'm fighting a cold right now, so I'm not thinking of any good reason why this is necessary, but I know that's how I did it on the 8568 MDS board.
Another possibility to consider is that the BDI's config that you are using is creating its own bad mappings.
Andy